SCL_H_2TAP_HARDCODE_COEF_EN  374 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 						SCL_H_2TAP_HARDCODE_COEF_EN, 0);
SCL_H_2TAP_HARDCODE_COEF_EN  188 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
SCL_H_2TAP_HARDCODE_COEF_EN  281 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
SCL_H_2TAP_HARDCODE_COEF_EN  373 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	type SCL_H_2TAP_HARDCODE_COEF_EN; \
SCL_H_2TAP_HARDCODE_COEF_EN  223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
SCL_H_2TAP_HARDCODE_COEF_EN  507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type SCL_H_2TAP_HARDCODE_COEF_EN; \
SCL_H_2TAP_HARDCODE_COEF_EN  326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 		SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,