SCLK_UART2        647 drivers/clk/rockchip/clk-px30.c 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
SCLK_UART2        156 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        193 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        266 drivers/clk/rockchip/clk-rk3188.c 	MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
SCLK_UART2        207 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        265 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        357 drivers/clk/rockchip/clk-rk3308.c 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
SCLK_UART2        260 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        407 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        268 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        175 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
SCLK_UART2        775 drivers/clk/samsung/clk-exynos7.c 	GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
SCLK_UART2        596 drivers/clk/samsung/clk-s5pv210.c 	GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,