SCLK_UART1        634 drivers/clk/rockchip/clk-px30.c 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
SCLK_UART1        152 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        189 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        262 drivers/clk/rockchip/clk-rk3188.c 	MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
SCLK_UART1        203 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        261 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        347 drivers/clk/rockchip/clk-rk3308.c 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
SCLK_UART1        256 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        261 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        264 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        171 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
SCLK_UART1        773 drivers/clk/samsung/clk-exynos7.c 	GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
SCLK_UART1        598 drivers/clk/samsung/clk-s5pv210.c 	GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,