SCLK_UART0        148 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        185 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        258 drivers/clk/rockchip/clk-rk3188.c 	MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
SCLK_UART0        199 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        257 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        337 drivers/clk/rockchip/clk-rk3308.c 	GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
SCLK_UART0        252 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        257 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        260 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        167 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
SCLK_UART0        668 drivers/clk/samsung/clk-exynos7.c 	GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
SCLK_UART0        600 drivers/clk/samsung/clk-s5pv210.c 	GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,