Rm                449 arch/arm64/include/asm/insn.h 			  enum aarch64_insn_register Rm,
Rm               1634 arch/arm64/kernel/insn.c 			  enum aarch64_insn_register Rm,
Rm               1662 arch/arm64/kernel/insn.c 	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
Rm                 56 arch/arm64/net/bpf_jit.h #define A64_LS_REG(Rt, Rn, Rm, size, type) \
Rm                 57 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
Rm                141 arch/arm64/net/bpf_jit.h #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
Rm                142 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
Rm                145 arch/arm64/net/bpf_jit.h #define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
Rm                146 arch/arm64/net/bpf_jit.h #define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
Rm                147 arch/arm64/net/bpf_jit.h #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
Rm                149 arch/arm64/net/bpf_jit.h #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
Rm                151 arch/arm64/net/bpf_jit.h #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
Rm                163 arch/arm64/net/bpf_jit.h #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
Rm                165 arch/arm64/net/bpf_jit.h #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
Rm                166 arch/arm64/net/bpf_jit.h #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
Rm                167 arch/arm64/net/bpf_jit.h #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
Rm                168 arch/arm64/net/bpf_jit.h #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
Rm                172 arch/arm64/net/bpf_jit.h #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
Rm                175 arch/arm64/net/bpf_jit.h #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
Rm                178 arch/arm64/net/bpf_jit.h #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
Rm                181 arch/arm64/net/bpf_jit.h #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
Rm                182 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
Rm                185 arch/arm64/net/bpf_jit.h #define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
Rm                186 arch/arm64/net/bpf_jit.h #define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
Rm                187 arch/arm64/net/bpf_jit.h #define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
Rm                188 arch/arm64/net/bpf_jit.h #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
Rm                190 arch/arm64/net/bpf_jit.h #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
Rm                160 arch/sh/math-emu/math.c 		READ(FRn, Rm + R0 + 4);
Rm                162 arch/sh/math-emu/math.c 		READ(FRn, Rm + R0);
Rm                164 arch/sh/math-emu/math.c 		READ(FRn, Rm + R0);
Rm                176 arch/sh/math-emu/math.c 		READ(FRn, Rm + 4);
Rm                178 arch/sh/math-emu/math.c 		READ(FRn, Rm);
Rm                180 arch/sh/math-emu/math.c 		READ(FRn, Rm);
Rm                192 arch/sh/math-emu/math.c 		READ(FRn, Rm + 4);
Rm                194 arch/sh/math-emu/math.c 		READ(FRn, Rm);
Rm                195 arch/sh/math-emu/math.c 		Rm += 8;
Rm                197 arch/sh/math-emu/math.c 		READ(FRn, Rm);
Rm                198 arch/sh/math-emu/math.c 		Rm += 4;