R_IMR_MAILBOX_CPU 31 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), R_IMR_MAILBOX_CPU 32 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)