R_IMR_MAILBOX_CLR_CPU  256 arch/mips/sibyte/sb1250/irq.c 		     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
R_IMR_MAILBOX_CLR_CPU  258 arch/mips/sibyte/sb1250/irq.c 		     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
R_IMR_MAILBOX_CLR_CPU   26 arch/mips/sibyte/sb1250/smp.c 	IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
R_IMR_MAILBOX_CLR_CPU   27 arch/mips/sibyte/sb1250/smp.c 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)