R_BCM1480_IMR_MAILBOX_0_SET_CPU   26 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
R_BCM1480_IMR_MAILBOX_0_SET_CPU   27 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
R_BCM1480_IMR_MAILBOX_0_SET_CPU   28 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
R_BCM1480_IMR_MAILBOX_0_SET_CPU   29 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),