R_BCM1480_IMR_MAILBOX_0_CPU  421 arch/mips/include/asm/sibyte/bcm1480_regs.h      (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
R_BCM1480_IMR_MAILBOX_0_CPU   40 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
R_BCM1480_IMR_MAILBOX_0_CPU   41 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
R_BCM1480_IMR_MAILBOX_0_CPU   42 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
R_BCM1480_IMR_MAILBOX_0_CPU   43 arch/mips/sibyte/bcm1480/smp.c 	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),