R_000100_MC_PT0_CNTL  525 drivers/gpu/drm/radeon/rs600.c 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
R_000100_MC_PT0_CNTL  527 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
R_000100_MC_PT0_CNTL  529 drivers/gpu/drm/radeon/rs600.c 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
R_000100_MC_PT0_CNTL  531 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
R_000100_MC_PT0_CNTL  533 drivers/gpu/drm/radeon/rs600.c 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
R_000100_MC_PT0_CNTL  535 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
R_000100_MC_PT0_CNTL  536 drivers/gpu/drm/radeon/rs600.c 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
R_000100_MC_PT0_CNTL  572 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL,
R_000100_MC_PT0_CNTL  608 drivers/gpu/drm/radeon/rs600.c 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
R_000100_MC_PT0_CNTL  609 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
R_000100_MC_PT0_CNTL  625 drivers/gpu/drm/radeon/rs600.c 	WREG32_MC(R_000100_MC_PT0_CNTL, 0);