RY                592 arch/powerpc/xmon/ppc-opc.c #define RZ RY
RY                596 arch/powerpc/xmon/ppc-opc.c #define ARY RY + 1
RY               7000 arch/powerpc/xmon/ppc-opc.c {"se_mr",	SE_RR(0,1),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7001 arch/powerpc/xmon/ppc-opc.c {"se_mtar",	SE_RR(0,2),	SE_RR_MASK,	PPCVLE,	0,		{ARX, RY}},
RY               7003 arch/powerpc/xmon/ppc-opc.c {"se_add",	SE_RR(1,0),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7004 arch/powerpc/xmon/ppc-opc.c {"se_mullw",	SE_RR(1,1),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7005 arch/powerpc/xmon/ppc-opc.c {"se_sub",	SE_RR(1,2),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7006 arch/powerpc/xmon/ppc-opc.c {"se_subf",	SE_RR(1,3),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7007 arch/powerpc/xmon/ppc-opc.c {"se_cmp",	SE_RR(3,0),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7008 arch/powerpc/xmon/ppc-opc.c {"se_cmpl",	SE_RR(3,1),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7009 arch/powerpc/xmon/ppc-opc.c {"se_cmph",	SE_RR(3,2),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7010 arch/powerpc/xmon/ppc-opc.c {"se_cmphl",	SE_RR(3,3),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7068 arch/powerpc/xmon/ppc-opc.c {"se_srw",	SE_RR(16,0),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7069 arch/powerpc/xmon/ppc-opc.c {"se_sraw",	SE_RR(16,1),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7070 arch/powerpc/xmon/ppc-opc.c {"se_slw",	SE_RR(16,2),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7072 arch/powerpc/xmon/ppc-opc.c {"se_or",	SE_RR(17,0),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7073 arch/powerpc/xmon/ppc-opc.c {"se_andc",	SE_RR(17,1),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7074 arch/powerpc/xmon/ppc-opc.c {"se_and",	SE_RR(17,2),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},
RY               7075 arch/powerpc/xmon/ppc-opc.c {"se_and.",	SE_RR(17,3),	SE_RR_MASK,	PPCVLE,	0,		{RX, RY}},