RTC_REG_A          40 arch/arm/mach-footbridge/isa-rtc.c 	CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);
RTC_REG_A          50 arch/arm/mach-footbridge/isa-rtc.c 	if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&
RTC_REG_A          38 arch/mips/kernel/cevt-ds1287.c 	CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
RTC_REG_A          83 arch/mips/mti-malta/malta-time.c 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
RTC_REG_A          84 arch/mips/mti-malta/malta-time.c 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
RTC_REG_A          90 arch/mips/mti-malta/malta-time.c 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
RTC_REG_A          94 arch/mips/mti-malta/malta-time.c 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
RTC_REG_A         100 arch/mips/mti-malta/malta-time.c 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
RTC_REG_A          74 include/linux/mc146818rtc.h #define RTC_FREQ_SELECT	RTC_REG_A