RT 51 arch/arm/boot/dts/st-pincfg.h #define SE_NICLK_IO (RT) RT 56 arch/arm/boot/dts/st-pincfg.h #define SE_ICLK_IO (RT | INVERTCLK) RT 61 arch/arm/boot/dts/st-pincfg.h #define DE_IO (RT | DOUBLE_EDGE) RT 66 arch/arm/boot/dts/st-pincfg.h #define ICLK (RT | CLKNOTDATA | INVERTCLK) RT 71 arch/arm/boot/dts/st-pincfg.h #define NICLK (RT | CLKNOTDATA) RT 555 arch/mips/kernel/traps.c regs->regs[(opcode & RT) >> 16] = value; RT 578 arch/mips/kernel/traps.c reg = (opcode & RT) >> 16; RT 667 arch/mips/kernel/traps.c int rt = (opcode & RT) >> 16; RT 43 arch/mips/mm/uasm-micromips.c [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD}, RT 44 arch/mips/mm/uasm-micromips.c [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 45 arch/mips/mm/uasm-micromips.c [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD}, RT 46 arch/mips/mm/uasm-micromips.c [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RT 47 arch/mips/mm/uasm-micromips.c [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 53 arch/mips/mm/uasm-micromips.c [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM}, RT 54 arch/mips/mm/uasm-micromips.c [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM}, RT 55 arch/mips/mm/uasm-micromips.c [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS}, RT 57 arch/mips/mm/uasm-micromips.c [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS}, RT 62 arch/mips/mm/uasm-micromips.c [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS}, RT 74 arch/mips/mm/uasm-micromips.c [insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE}, RT 75 arch/mips/mm/uasm-micromips.c [insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE}, RT 78 arch/mips/mm/uasm-micromips.c [insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS}, RT 80 arch/mips/mm/uasm-micromips.c [insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 82 arch/mips/mm/uasm-micromips.c [insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 83 arch/mips/mm/uasm-micromips.c [insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM}, RT 86 arch/mips/mm/uasm-micromips.c [insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 87 arch/mips/mm/uasm-micromips.c [insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD}, RT 90 arch/mips/mm/uasm-micromips.c [insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD}, RT 93 arch/mips/mm/uasm-micromips.c [insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD}, RT 94 arch/mips/mm/uasm-micromips.c [insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD}, RT 95 arch/mips/mm/uasm-micromips.c [insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RT 96 arch/mips/mm/uasm-micromips.c [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM}, RT 98 arch/mips/mm/uasm-micromips.c [insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM}, RT 101 arch/mips/mm/uasm-micromips.c [insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD}, RT 102 arch/mips/mm/uasm-micromips.c [insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD}, RT 103 arch/mips/mm/uasm-micromips.c [insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD}, RT 104 arch/mips/mm/uasm-micromips.c [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 105 arch/mips/mm/uasm-micromips.c [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD}, RT 106 arch/mips/mm/uasm-micromips.c [insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD}, RT 107 arch/mips/mm/uasm-micromips.c [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD}, RT 108 arch/mips/mm/uasm-micromips.c [insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD}, RT 109 arch/mips/mm/uasm-micromips.c [insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD}, RT 110 arch/mips/mm/uasm-micromips.c [insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD}, RT 111 arch/mips/mm/uasm-micromips.c [insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD}, RT 112 arch/mips/mm/uasm-micromips.c [insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RT 119 arch/mips/mm/uasm-micromips.c [insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS}, RT 120 arch/mips/mm/uasm-micromips.c [insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD}, RT 121 arch/mips/mm/uasm-micromips.c [insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RT 178 arch/mips/mm/uasm-micromips.c if (ip->fields & RT) { RT 51 arch/mips/mm/uasm-mips.c [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 52 arch/mips/mm/uasm-mips.c [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, RT 53 arch/mips/mm/uasm-mips.c [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, RT 54 arch/mips/mm/uasm-mips.c [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RT 55 arch/mips/mm/uasm-mips.c [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 56 arch/mips/mm/uasm-mips.c [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 57 arch/mips/mm/uasm-mips.c [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 58 arch/mips/mm/uasm-mips.c [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 65 arch/mips/mm/uasm-mips.c [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RT 68 arch/mips/mm/uasm-mips.c [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 70 arch/mips/mm/uasm-mips.c [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, RT 72 arch/mips/mm/uasm-mips.c [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD}, RT 74 arch/mips/mm/uasm-mips.c [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD}, RT 76 arch/mips/mm/uasm-mips.c [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 77 arch/mips/mm/uasm-mips.c [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, RT 78 arch/mips/mm/uasm-mips.c [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, RT 80 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 81 arch/mips/mm/uasm-mips.c [insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT}, RT 82 arch/mips/mm/uasm-mips.c [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, RT 83 arch/mips/mm/uasm-mips.c [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, RT 84 arch/mips/mm/uasm-mips.c [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, RT 85 arch/mips/mm/uasm-mips.c [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, RT 87 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 88 arch/mips/mm/uasm-mips.c [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, RT 90 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 91 arch/mips/mm/uasm-mips.c [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, RT 92 arch/mips/mm/uasm-mips.c [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, RT 94 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 95 arch/mips/mm/uasm-mips.c [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, RT 96 arch/mips/mm/uasm-mips.c [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, RT 97 arch/mips/mm/uasm-mips.c [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD}, RT 98 arch/mips/mm/uasm-mips.c [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD}, RT 99 arch/mips/mm/uasm-mips.c [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE}, RT 100 arch/mips/mm/uasm-mips.c [insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE}, RT 101 arch/mips/mm/uasm-mips.c [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD}, RT 102 arch/mips/mm/uasm-mips.c [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE}, RT 103 arch/mips/mm/uasm-mips.c [insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE}, RT 104 arch/mips/mm/uasm-mips.c [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD}, RT 105 arch/mips/mm/uasm-mips.c [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE}, RT 106 arch/mips/mm/uasm-mips.c [insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE}, RT 107 arch/mips/mm/uasm-mips.c [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD}, RT 108 arch/mips/mm/uasm-mips.c [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD}, RT 110 arch/mips/mm/uasm-mips.c [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE}, RT 111 arch/mips/mm/uasm-mips.c [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE}, RT 120 arch/mips/mm/uasm-mips.c [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 121 arch/mips/mm/uasm-mips.c [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 122 arch/mips/mm/uasm-mips.c [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 123 arch/mips/mm/uasm-mips.c [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD}, RT 125 arch/mips/mm/uasm-mips.c [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD}, RT 126 arch/mips/mm/uasm-mips.c [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 127 arch/mips/mm/uasm-mips.c [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 129 arch/mips/mm/uasm-mips.c [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 130 arch/mips/mm/uasm-mips.c [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 132 arch/mips/mm/uasm-mips.c [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, RT 133 arch/mips/mm/uasm-mips.c [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, RT 135 arch/mips/mm/uasm-mips.c [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM}, RT 136 arch/mips/mm/uasm-mips.c [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 137 arch/mips/mm/uasm-mips.c [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 138 arch/mips/mm/uasm-mips.c [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD}, RT 139 arch/mips/mm/uasm-mips.c [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, RT 140 arch/mips/mm/uasm-mips.c [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, RT 144 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 145 arch/mips/mm/uasm-mips.c [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, RT 146 arch/mips/mm/uasm-mips.c [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD}, RT 147 arch/mips/mm/uasm-mips.c [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, RT 148 arch/mips/mm/uasm-mips.c [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, RT 152 arch/mips/mm/uasm-mips.c RS | RT | RD}, RT 154 arch/mips/mm/uasm-mips.c [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, RT 156 arch/mips/mm/uasm-mips.c [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD}, RT 158 arch/mips/mm/uasm-mips.c [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT}, RT 159 arch/mips/mm/uasm-mips.c [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD}, RT 160 arch/mips/mm/uasm-mips.c [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD}, RT 161 arch/mips/mm/uasm-mips.c [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RT 163 arch/mips/mm/uasm-mips.c [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 165 arch/mips/mm/uasm-mips.c [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, RT 168 arch/mips/mm/uasm-mips.c [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE}, RT 169 arch/mips/mm/uasm-mips.c [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 171 arch/mips/mm/uasm-mips.c [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 172 arch/mips/mm/uasm-mips.c [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 174 arch/mips/mm/uasm-mips.c [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, RT 175 arch/mips/mm/uasm-mips.c [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9}, RT 177 arch/mips/mm/uasm-mips.c [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 178 arch/mips/mm/uasm-mips.c [insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD}, RT 179 arch/mips/mm/uasm-mips.c [insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD}, RT 180 arch/mips/mm/uasm-mips.c [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 181 arch/mips/mm/uasm-mips.c [insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE}, RT 182 arch/mips/mm/uasm-mips.c [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD}, RT 183 arch/mips/mm/uasm-mips.c [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD}, RT 184 arch/mips/mm/uasm-mips.c [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 185 arch/mips/mm/uasm-mips.c [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 186 arch/mips/mm/uasm-mips.c [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, RT 187 arch/mips/mm/uasm-mips.c [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE}, RT 188 arch/mips/mm/uasm-mips.c [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD}, RT 189 arch/mips/mm/uasm-mips.c [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE}, RT 190 arch/mips/mm/uasm-mips.c [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, RT 191 arch/mips/mm/uasm-mips.c [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD}, RT 192 arch/mips/mm/uasm-mips.c [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RT 200 arch/mips/mm/uasm-mips.c [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD}, RT 201 arch/mips/mm/uasm-mips.c [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD}, RT 202 arch/mips/mm/uasm-mips.c [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RT 247 arch/mips/mm/uasm-mips.c if (ip->fields & RT) RT 488 arch/nds32/mm/alignment.c *idx_to_addr(regs, RT(inst)) = RT 491 arch/nds32/mm/alignment.c *idx_to_addr(regs, RT(inst)) = target_val; RT 497 arch/nds32/mm/alignment.c target_val = *idx_to_addr(regs, RT(inst)); RT 3101 arch/powerpc/xmon/ppc-opc.c {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3102 arch/powerpc/xmon/ppc-opc.c {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3108 arch/powerpc/xmon/ppc-opc.c {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3110 arch/powerpc/xmon/ppc-opc.c {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3142 arch/powerpc/xmon/ppc-opc.c {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RT 3144 arch/powerpc/xmon/ppc-opc.c {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RT 3147 arch/powerpc/xmon/ppc-opc.c {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RT 3177 arch/powerpc/xmon/ppc-opc.c {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3179 arch/powerpc/xmon/ppc-opc.c {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3180 arch/powerpc/xmon/ppc-opc.c {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3181 arch/powerpc/xmon/ppc-opc.c {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3182 arch/powerpc/xmon/ppc-opc.c {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3183 arch/powerpc/xmon/ppc-opc.c {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3197 arch/powerpc/xmon/ppc-opc.c {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3198 arch/powerpc/xmon/ppc-opc.c {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3207 arch/powerpc/xmon/ppc-opc.c {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3208 arch/powerpc/xmon/ppc-opc.c {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3209 arch/powerpc/xmon/ppc-opc.c {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3210 arch/powerpc/xmon/ppc-opc.c {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3220 arch/powerpc/xmon/ppc-opc.c {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3222 arch/powerpc/xmon/ppc-opc.c {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3223 arch/powerpc/xmon/ppc-opc.c {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3224 arch/powerpc/xmon/ppc-opc.c {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3233 arch/powerpc/xmon/ppc-opc.c {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3234 arch/powerpc/xmon/ppc-opc.c {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3235 arch/powerpc/xmon/ppc-opc.c {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3236 arch/powerpc/xmon/ppc-opc.c {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3237 arch/powerpc/xmon/ppc-opc.c {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3238 arch/powerpc/xmon/ppc-opc.c {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3248 arch/powerpc/xmon/ppc-opc.c {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3249 arch/powerpc/xmon/ppc-opc.c {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3256 arch/powerpc/xmon/ppc-opc.c {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3257 arch/powerpc/xmon/ppc-opc.c {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3258 arch/powerpc/xmon/ppc-opc.c {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3259 arch/powerpc/xmon/ppc-opc.c {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3293 arch/powerpc/xmon/ppc-opc.c {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, RT 3316 arch/powerpc/xmon/ppc-opc.c {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, RT 3327 arch/powerpc/xmon/ppc-opc.c {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, RT 3329 arch/powerpc/xmon/ppc-opc.c {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, RT 3447 arch/powerpc/xmon/ppc-opc.c {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3449 arch/powerpc/xmon/ppc-opc.c {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3455 arch/powerpc/xmon/ppc-opc.c {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3457 arch/powerpc/xmon/ppc-opc.c {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3486 arch/powerpc/xmon/ppc-opc.c {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3487 arch/powerpc/xmon/ppc-opc.c {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RT 3488 arch/powerpc/xmon/ppc-opc.c {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3489 arch/powerpc/xmon/ppc-opc.c {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3490 arch/powerpc/xmon/ppc-opc.c {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3491 arch/powerpc/xmon/ppc-opc.c {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3501 arch/powerpc/xmon/ppc-opc.c {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3502 arch/powerpc/xmon/ppc-opc.c {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3511 arch/powerpc/xmon/ppc-opc.c {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3512 arch/powerpc/xmon/ppc-opc.c {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3513 arch/powerpc/xmon/ppc-opc.c {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3514 arch/powerpc/xmon/ppc-opc.c {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3535 arch/powerpc/xmon/ppc-opc.c {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3536 arch/powerpc/xmon/ppc-opc.c {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3566 arch/powerpc/xmon/ppc-opc.c {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3568 arch/powerpc/xmon/ppc-opc.c {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3571 arch/powerpc/xmon/ppc-opc.c {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3572 arch/powerpc/xmon/ppc-opc.c {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3595 arch/powerpc/xmon/ppc-opc.c {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3596 arch/powerpc/xmon/ppc-opc.c {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3619 arch/powerpc/xmon/ppc-opc.c {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3620 arch/powerpc/xmon/ppc-opc.c {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3621 arch/powerpc/xmon/ppc-opc.c {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3622 arch/powerpc/xmon/ppc-opc.c {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3648 arch/powerpc/xmon/ppc-opc.c {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3649 arch/powerpc/xmon/ppc-opc.c {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3672 arch/powerpc/xmon/ppc-opc.c {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3674 arch/powerpc/xmon/ppc-opc.c {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3677 arch/powerpc/xmon/ppc-opc.c {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3678 arch/powerpc/xmon/ppc-opc.c {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3704 arch/powerpc/xmon/ppc-opc.c {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3705 arch/powerpc/xmon/ppc-opc.c {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3725 arch/powerpc/xmon/ppc-opc.c {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3727 arch/powerpc/xmon/ppc-opc.c {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3730 arch/powerpc/xmon/ppc-opc.c {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3731 arch/powerpc/xmon/ppc-opc.c {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3733 arch/powerpc/xmon/ppc-opc.c {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, RT 3734 arch/powerpc/xmon/ppc-opc.c {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, RT 3754 arch/powerpc/xmon/ppc-opc.c {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3761 arch/powerpc/xmon/ppc-opc.c {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3771 arch/powerpc/xmon/ppc-opc.c {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3787 arch/powerpc/xmon/ppc-opc.c {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3788 arch/powerpc/xmon/ppc-opc.c {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3789 arch/powerpc/xmon/ppc-opc.c {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3795 arch/powerpc/xmon/ppc-opc.c {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3798 arch/powerpc/xmon/ppc-opc.c {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3799 arch/powerpc/xmon/ppc-opc.c {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3800 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3801 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3810 arch/powerpc/xmon/ppc-opc.c {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RT 3811 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3812 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3819 arch/powerpc/xmon/ppc-opc.c {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3820 arch/powerpc/xmon/ppc-opc.c {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3821 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3822 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RT 3825 arch/powerpc/xmon/ppc-opc.c {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RT 3826 arch/powerpc/xmon/ppc-opc.c {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RT 3828 arch/powerpc/xmon/ppc-opc.c {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RT 3829 arch/powerpc/xmon/ppc-opc.c {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RT 3831 arch/powerpc/xmon/ppc-opc.c {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, RT 3843 arch/powerpc/xmon/ppc-opc.c {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RT 3844 arch/powerpc/xmon/ppc-opc.c {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RT 3845 arch/powerpc/xmon/ppc-opc.c {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, RT 3847 arch/powerpc/xmon/ppc-opc.c {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RT 3848 arch/powerpc/xmon/ppc-opc.c {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RT 3849 arch/powerpc/xmon/ppc-opc.c {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, RT 3851 arch/powerpc/xmon/ppc-opc.c {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, RT 3852 arch/powerpc/xmon/ppc-opc.c {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, RT 3853 arch/powerpc/xmon/ppc-opc.c {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, RT 3854 arch/powerpc/xmon/ppc-opc.c {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RT 3855 arch/powerpc/xmon/ppc-opc.c {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, RT 3856 arch/powerpc/xmon/ppc-opc.c {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, RT 3858 arch/powerpc/xmon/ppc-opc.c {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, RT 3859 arch/powerpc/xmon/ppc-opc.c {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, RT 3860 arch/powerpc/xmon/ppc-opc.c {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, RT 3861 arch/powerpc/xmon/ppc-opc.c {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, RT 3862 arch/powerpc/xmon/ppc-opc.c {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, RT 4149 arch/powerpc/xmon/ppc-opc.c {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, RT 4150 arch/powerpc/xmon/ppc-opc.c {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, RT 4699 arch/powerpc/xmon/ppc-opc.c {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4700 arch/powerpc/xmon/ppc-opc.c {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4701 arch/powerpc/xmon/ppc-opc.c {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RT 4702 arch/powerpc/xmon/ppc-opc.c {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4703 arch/powerpc/xmon/ppc-opc.c {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4704 arch/powerpc/xmon/ppc-opc.c {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RT 4706 arch/powerpc/xmon/ppc-opc.c {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 4707 arch/powerpc/xmon/ppc-opc.c {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 4709 arch/powerpc/xmon/ppc-opc.c {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4710 arch/powerpc/xmon/ppc-opc.c {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4711 arch/powerpc/xmon/ppc-opc.c {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4712 arch/powerpc/xmon/ppc-opc.c {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4714 arch/powerpc/xmon/ppc-opc.c {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4715 arch/powerpc/xmon/ppc-opc.c {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4719 arch/powerpc/xmon/ppc-opc.c {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RT 4726 arch/powerpc/xmon/ppc-opc.c {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, RT 4727 arch/powerpc/xmon/ppc-opc.c {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, RT 4729 arch/powerpc/xmon/ppc-opc.c {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, RT 4731 arch/powerpc/xmon/ppc-opc.c {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, RT 4735 arch/powerpc/xmon/ppc-opc.c {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RT 4736 arch/powerpc/xmon/ppc-opc.c {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4757 arch/powerpc/xmon/ppc-opc.c {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 4762 arch/powerpc/xmon/ppc-opc.c {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 4775 arch/powerpc/xmon/ppc-opc.c {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RT 4779 arch/powerpc/xmon/ppc-opc.c {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, RT 4783 arch/powerpc/xmon/ppc-opc.c {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RT 4785 arch/powerpc/xmon/ppc-opc.c {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, RT 4787 arch/powerpc/xmon/ppc-opc.c {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4788 arch/powerpc/xmon/ppc-opc.c {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RT 4789 arch/powerpc/xmon/ppc-opc.c {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4790 arch/powerpc/xmon/ppc-opc.c {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RT 4797 arch/powerpc/xmon/ppc-opc.c {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RT 4799 arch/powerpc/xmon/ppc-opc.c {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, RT 4803 arch/powerpc/xmon/ppc-opc.c {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, RT 4804 arch/powerpc/xmon/ppc-opc.c {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4836 arch/powerpc/xmon/ppc-opc.c {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 4837 arch/powerpc/xmon/ppc-opc.c {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 4839 arch/powerpc/xmon/ppc-opc.c {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4840 arch/powerpc/xmon/ppc-opc.c {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 4847 arch/powerpc/xmon/ppc-opc.c {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, RT 4849 arch/powerpc/xmon/ppc-opc.c {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, RT 4854 arch/powerpc/xmon/ppc-opc.c {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, RT 4856 arch/powerpc/xmon/ppc-opc.c {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 4863 arch/powerpc/xmon/ppc-opc.c {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, RT 4864 arch/powerpc/xmon/ppc-opc.c {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, RT 4866 arch/powerpc/xmon/ppc-opc.c {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 4867 arch/powerpc/xmon/ppc-opc.c {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 4877 arch/powerpc/xmon/ppc-opc.c {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RT 4881 arch/powerpc/xmon/ppc-opc.c {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, RT 4892 arch/powerpc/xmon/ppc-opc.c {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, RT 4901 arch/powerpc/xmon/ppc-opc.c {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4902 arch/powerpc/xmon/ppc-opc.c {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4903 arch/powerpc/xmon/ppc-opc.c {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4904 arch/powerpc/xmon/ppc-opc.c {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4906 arch/powerpc/xmon/ppc-opc.c {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4907 arch/powerpc/xmon/ppc-opc.c {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4908 arch/powerpc/xmon/ppc-opc.c {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 4909 arch/powerpc/xmon/ppc-opc.c {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 4924 arch/powerpc/xmon/ppc-opc.c {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RT 4925 arch/powerpc/xmon/ppc-opc.c {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RT 4953 arch/powerpc/xmon/ppc-opc.c {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, RT 4963 arch/powerpc/xmon/ppc-opc.c {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, RT 4985 arch/powerpc/xmon/ppc-opc.c {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 4986 arch/powerpc/xmon/ppc-opc.c {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 4987 arch/powerpc/xmon/ppc-opc.c {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 4988 arch/powerpc/xmon/ppc-opc.c {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 4990 arch/powerpc/xmon/ppc-opc.c {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 4991 arch/powerpc/xmon/ppc-opc.c {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 4992 arch/powerpc/xmon/ppc-opc.c {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 4993 arch/powerpc/xmon/ppc-opc.c {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5004 arch/powerpc/xmon/ppc-opc.c {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RT 5025 arch/powerpc/xmon/ppc-opc.c {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5026 arch/powerpc/xmon/ppc-opc.c {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5027 arch/powerpc/xmon/ppc-opc.c {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5028 arch/powerpc/xmon/ppc-opc.c {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5030 arch/powerpc/xmon/ppc-opc.c {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5031 arch/powerpc/xmon/ppc-opc.c {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5033 arch/powerpc/xmon/ppc-opc.c {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5034 arch/powerpc/xmon/ppc-opc.c {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5035 arch/powerpc/xmon/ppc-opc.c {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5036 arch/powerpc/xmon/ppc-opc.c {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5038 arch/powerpc/xmon/ppc-opc.c {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5039 arch/powerpc/xmon/ppc-opc.c {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5040 arch/powerpc/xmon/ppc-opc.c {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5041 arch/powerpc/xmon/ppc-opc.c {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5064 arch/powerpc/xmon/ppc-opc.c {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 5076 arch/powerpc/xmon/ppc-opc.c {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5077 arch/powerpc/xmon/ppc-opc.c {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5079 arch/powerpc/xmon/ppc-opc.c {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, RT 5081 arch/powerpc/xmon/ppc-opc.c {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5082 arch/powerpc/xmon/ppc-opc.c {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5083 arch/powerpc/xmon/ppc-opc.c {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5084 arch/powerpc/xmon/ppc-opc.c {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5086 arch/powerpc/xmon/ppc-opc.c {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, RT 5096 arch/powerpc/xmon/ppc-opc.c {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, RT 5100 arch/powerpc/xmon/ppc-opc.c {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, RT 5101 arch/powerpc/xmon/ppc-opc.c {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, RT 5108 arch/powerpc/xmon/ppc-opc.c {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, RT 5115 arch/powerpc/xmon/ppc-opc.c {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 5124 arch/powerpc/xmon/ppc-opc.c {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, RT 5133 arch/powerpc/xmon/ppc-opc.c {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, RT 5135 arch/powerpc/xmon/ppc-opc.c {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RT 5137 arch/powerpc/xmon/ppc-opc.c {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, RT 5144 arch/powerpc/xmon/ppc-opc.c {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RT 5146 arch/powerpc/xmon/ppc-opc.c {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, RT 5147 arch/powerpc/xmon/ppc-opc.c {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, RT 5148 arch/powerpc/xmon/ppc-opc.c {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, RT 5149 arch/powerpc/xmon/ppc-opc.c {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, RT 5150 arch/powerpc/xmon/ppc-opc.c {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, RT 5151 arch/powerpc/xmon/ppc-opc.c {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, RT 5152 arch/powerpc/xmon/ppc-opc.c {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, RT 5153 arch/powerpc/xmon/ppc-opc.c {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, RT 5154 arch/powerpc/xmon/ppc-opc.c {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, RT 5155 arch/powerpc/xmon/ppc-opc.c {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, RT 5156 arch/powerpc/xmon/ppc-opc.c {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, RT 5157 arch/powerpc/xmon/ppc-opc.c {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, RT 5158 arch/powerpc/xmon/ppc-opc.c {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, RT 5159 arch/powerpc/xmon/ppc-opc.c {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, RT 5160 arch/powerpc/xmon/ppc-opc.c {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, RT 5161 arch/powerpc/xmon/ppc-opc.c {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, RT 5162 arch/powerpc/xmon/ppc-opc.c {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, RT 5163 arch/powerpc/xmon/ppc-opc.c {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, RT 5164 arch/powerpc/xmon/ppc-opc.c {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, RT 5165 arch/powerpc/xmon/ppc-opc.c {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, RT 5166 arch/powerpc/xmon/ppc-opc.c {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, RT 5167 arch/powerpc/xmon/ppc-opc.c {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, RT 5168 arch/powerpc/xmon/ppc-opc.c {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, RT 5169 arch/powerpc/xmon/ppc-opc.c {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, RT 5170 arch/powerpc/xmon/ppc-opc.c {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, RT 5171 arch/powerpc/xmon/ppc-opc.c {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, RT 5172 arch/powerpc/xmon/ppc-opc.c {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, RT 5173 arch/powerpc/xmon/ppc-opc.c {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, RT 5174 arch/powerpc/xmon/ppc-opc.c {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, RT 5175 arch/powerpc/xmon/ppc-opc.c {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, RT 5176 arch/powerpc/xmon/ppc-opc.c {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, RT 5177 arch/powerpc/xmon/ppc-opc.c {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, RT 5178 arch/powerpc/xmon/ppc-opc.c {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, RT 5179 arch/powerpc/xmon/ppc-opc.c {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, RT 5180 arch/powerpc/xmon/ppc-opc.c {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, RT 5181 arch/powerpc/xmon/ppc-opc.c {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, RT 5185 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, RT 5187 arch/powerpc/xmon/ppc-opc.c {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5188 arch/powerpc/xmon/ppc-opc.c {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5192 arch/powerpc/xmon/ppc-opc.c {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, RT 5193 arch/powerpc/xmon/ppc-opc.c {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}}, RT 5197 arch/powerpc/xmon/ppc-opc.c {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, RT 5198 arch/powerpc/xmon/ppc-opc.c {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, RT 5199 arch/powerpc/xmon/ppc-opc.c {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, RT 5200 arch/powerpc/xmon/ppc-opc.c {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, RT 5201 arch/powerpc/xmon/ppc-opc.c {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, RT 5202 arch/powerpc/xmon/ppc-opc.c {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, RT 5203 arch/powerpc/xmon/ppc-opc.c {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, RT 5204 arch/powerpc/xmon/ppc-opc.c {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, RT 5205 arch/powerpc/xmon/ppc-opc.c {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, RT 5206 arch/powerpc/xmon/ppc-opc.c {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, RT 5207 arch/powerpc/xmon/ppc-opc.c {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, RT 5208 arch/powerpc/xmon/ppc-opc.c {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, RT 5209 arch/powerpc/xmon/ppc-opc.c {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, RT 5210 arch/powerpc/xmon/ppc-opc.c {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, RT 5211 arch/powerpc/xmon/ppc-opc.c {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, RT 5212 arch/powerpc/xmon/ppc-opc.c {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, RT 5213 arch/powerpc/xmon/ppc-opc.c {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, RT 5214 arch/powerpc/xmon/ppc-opc.c {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, RT 5215 arch/powerpc/xmon/ppc-opc.c {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, RT 5216 arch/powerpc/xmon/ppc-opc.c {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, RT 5217 arch/powerpc/xmon/ppc-opc.c {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, RT 5218 arch/powerpc/xmon/ppc-opc.c {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, RT 5219 arch/powerpc/xmon/ppc-opc.c {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, RT 5220 arch/powerpc/xmon/ppc-opc.c {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, RT 5221 arch/powerpc/xmon/ppc-opc.c {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, RT 5222 arch/powerpc/xmon/ppc-opc.c {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, RT 5223 arch/powerpc/xmon/ppc-opc.c {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, RT 5224 arch/powerpc/xmon/ppc-opc.c {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, RT 5225 arch/powerpc/xmon/ppc-opc.c {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, RT 5226 arch/powerpc/xmon/ppc-opc.c {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, RT 5227 arch/powerpc/xmon/ppc-opc.c {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, RT 5228 arch/powerpc/xmon/ppc-opc.c {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, RT 5229 arch/powerpc/xmon/ppc-opc.c {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, RT 5230 arch/powerpc/xmon/ppc-opc.c {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, RT 5231 arch/powerpc/xmon/ppc-opc.c {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, RT 5232 arch/powerpc/xmon/ppc-opc.c {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, RT 5233 arch/powerpc/xmon/ppc-opc.c {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, RT 5234 arch/powerpc/xmon/ppc-opc.c {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, RT 5235 arch/powerpc/xmon/ppc-opc.c {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, RT 5236 arch/powerpc/xmon/ppc-opc.c {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, RT 5237 arch/powerpc/xmon/ppc-opc.c {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, RT 5238 arch/powerpc/xmon/ppc-opc.c {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, RT 5239 arch/powerpc/xmon/ppc-opc.c {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, RT 5240 arch/powerpc/xmon/ppc-opc.c {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, RT 5241 arch/powerpc/xmon/ppc-opc.c {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, RT 5242 arch/powerpc/xmon/ppc-opc.c {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, RT 5243 arch/powerpc/xmon/ppc-opc.c {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, RT 5244 arch/powerpc/xmon/ppc-opc.c {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, RT 5245 arch/powerpc/xmon/ppc-opc.c {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, RT 5246 arch/powerpc/xmon/ppc-opc.c {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, RT 5247 arch/powerpc/xmon/ppc-opc.c {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, RT 5248 arch/powerpc/xmon/ppc-opc.c {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, RT 5249 arch/powerpc/xmon/ppc-opc.c {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, RT 5250 arch/powerpc/xmon/ppc-opc.c {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, RT 5251 arch/powerpc/xmon/ppc-opc.c {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, RT 5252 arch/powerpc/xmon/ppc-opc.c {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, RT 5253 arch/powerpc/xmon/ppc-opc.c {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, RT 5254 arch/powerpc/xmon/ppc-opc.c {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, RT 5255 arch/powerpc/xmon/ppc-opc.c {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, RT 5256 arch/powerpc/xmon/ppc-opc.c {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, RT 5257 arch/powerpc/xmon/ppc-opc.c {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, RT 5258 arch/powerpc/xmon/ppc-opc.c {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, RT 5259 arch/powerpc/xmon/ppc-opc.c {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, RT 5260 arch/powerpc/xmon/ppc-opc.c {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, RT 5261 arch/powerpc/xmon/ppc-opc.c {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, RT 5262 arch/powerpc/xmon/ppc-opc.c {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, RT 5263 arch/powerpc/xmon/ppc-opc.c {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, RT 5264 arch/powerpc/xmon/ppc-opc.c {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, RT 5265 arch/powerpc/xmon/ppc-opc.c {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, RT 5266 arch/powerpc/xmon/ppc-opc.c {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, RT 5267 arch/powerpc/xmon/ppc-opc.c {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, RT 5268 arch/powerpc/xmon/ppc-opc.c {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, RT 5269 arch/powerpc/xmon/ppc-opc.c {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, RT 5270 arch/powerpc/xmon/ppc-opc.c {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, RT 5271 arch/powerpc/xmon/ppc-opc.c {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, RT 5272 arch/powerpc/xmon/ppc-opc.c {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, RT 5273 arch/powerpc/xmon/ppc-opc.c {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, RT 5274 arch/powerpc/xmon/ppc-opc.c {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, RT 5275 arch/powerpc/xmon/ppc-opc.c {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, RT 5276 arch/powerpc/xmon/ppc-opc.c {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, RT 5277 arch/powerpc/xmon/ppc-opc.c {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, RT 5278 arch/powerpc/xmon/ppc-opc.c {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, RT 5279 arch/powerpc/xmon/ppc-opc.c {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, RT 5280 arch/powerpc/xmon/ppc-opc.c {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, RT 5281 arch/powerpc/xmon/ppc-opc.c {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, RT 5282 arch/powerpc/xmon/ppc-opc.c {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, RT 5283 arch/powerpc/xmon/ppc-opc.c {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, RT 5284 arch/powerpc/xmon/ppc-opc.c {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, RT 5285 arch/powerpc/xmon/ppc-opc.c {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, RT 5286 arch/powerpc/xmon/ppc-opc.c {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, RT 5287 arch/powerpc/xmon/ppc-opc.c {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, RT 5288 arch/powerpc/xmon/ppc-opc.c {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, RT 5289 arch/powerpc/xmon/ppc-opc.c {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, RT 5290 arch/powerpc/xmon/ppc-opc.c {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, RT 5291 arch/powerpc/xmon/ppc-opc.c {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, RT 5292 arch/powerpc/xmon/ppc-opc.c {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, RT 5293 arch/powerpc/xmon/ppc-opc.c {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, RT 5294 arch/powerpc/xmon/ppc-opc.c {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, RT 5295 arch/powerpc/xmon/ppc-opc.c {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, RT 5296 arch/powerpc/xmon/ppc-opc.c {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, RT 5297 arch/powerpc/xmon/ppc-opc.c {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, RT 5298 arch/powerpc/xmon/ppc-opc.c {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, RT 5299 arch/powerpc/xmon/ppc-opc.c {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, RT 5300 arch/powerpc/xmon/ppc-opc.c {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, RT 5301 arch/powerpc/xmon/ppc-opc.c {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, RT 5302 arch/powerpc/xmon/ppc-opc.c {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, RT 5303 arch/powerpc/xmon/ppc-opc.c {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, RT 5304 arch/powerpc/xmon/ppc-opc.c {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, RT 5305 arch/powerpc/xmon/ppc-opc.c {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, RT 5306 arch/powerpc/xmon/ppc-opc.c {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, RT 5307 arch/powerpc/xmon/ppc-opc.c {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, RT 5308 arch/powerpc/xmon/ppc-opc.c {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, RT 5309 arch/powerpc/xmon/ppc-opc.c {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, RT 5310 arch/powerpc/xmon/ppc-opc.c {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, RT 5311 arch/powerpc/xmon/ppc-opc.c {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, RT 5312 arch/powerpc/xmon/ppc-opc.c {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, RT 5313 arch/powerpc/xmon/ppc-opc.c {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, RT 5314 arch/powerpc/xmon/ppc-opc.c {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, RT 5315 arch/powerpc/xmon/ppc-opc.c {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, RT 5316 arch/powerpc/xmon/ppc-opc.c {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, RT 5317 arch/powerpc/xmon/ppc-opc.c {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, RT 5318 arch/powerpc/xmon/ppc-opc.c {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, RT 5319 arch/powerpc/xmon/ppc-opc.c {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, RT 5320 arch/powerpc/xmon/ppc-opc.c {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, RT 5321 arch/powerpc/xmon/ppc-opc.c {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, RT 5322 arch/powerpc/xmon/ppc-opc.c {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, RT 5323 arch/powerpc/xmon/ppc-opc.c {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, RT 5324 arch/powerpc/xmon/ppc-opc.c {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, RT 5325 arch/powerpc/xmon/ppc-opc.c {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, RT 5326 arch/powerpc/xmon/ppc-opc.c {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, RT 5327 arch/powerpc/xmon/ppc-opc.c {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, RT 5328 arch/powerpc/xmon/ppc-opc.c {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, RT 5329 arch/powerpc/xmon/ppc-opc.c {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, RT 5330 arch/powerpc/xmon/ppc-opc.c {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, RT 5331 arch/powerpc/xmon/ppc-opc.c {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, RT 5332 arch/powerpc/xmon/ppc-opc.c {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, RT 5333 arch/powerpc/xmon/ppc-opc.c {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, RT 5334 arch/powerpc/xmon/ppc-opc.c {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, RT 5335 arch/powerpc/xmon/ppc-opc.c {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, RT 5336 arch/powerpc/xmon/ppc-opc.c {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, RT 5337 arch/powerpc/xmon/ppc-opc.c {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, RT 5338 arch/powerpc/xmon/ppc-opc.c {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, RT 5339 arch/powerpc/xmon/ppc-opc.c {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, RT 5340 arch/powerpc/xmon/ppc-opc.c {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, RT 5341 arch/powerpc/xmon/ppc-opc.c {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, RT 5342 arch/powerpc/xmon/ppc-opc.c {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, RT 5343 arch/powerpc/xmon/ppc-opc.c {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, RT 5344 arch/powerpc/xmon/ppc-opc.c {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, RT 5345 arch/powerpc/xmon/ppc-opc.c {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, RT 5346 arch/powerpc/xmon/ppc-opc.c {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, RT 5347 arch/powerpc/xmon/ppc-opc.c {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, RT 5348 arch/powerpc/xmon/ppc-opc.c {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, RT 5349 arch/powerpc/xmon/ppc-opc.c {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, RT 5350 arch/powerpc/xmon/ppc-opc.c {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, RT 5351 arch/powerpc/xmon/ppc-opc.c {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, RT 5352 arch/powerpc/xmon/ppc-opc.c {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, RT 5353 arch/powerpc/xmon/ppc-opc.c {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, RT 5354 arch/powerpc/xmon/ppc-opc.c {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, RT 5355 arch/powerpc/xmon/ppc-opc.c {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, RT 5356 arch/powerpc/xmon/ppc-opc.c {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, RT 5357 arch/powerpc/xmon/ppc-opc.c {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, RT 5358 arch/powerpc/xmon/ppc-opc.c {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, RT 5359 arch/powerpc/xmon/ppc-opc.c {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, RT 5360 arch/powerpc/xmon/ppc-opc.c {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, RT 5361 arch/powerpc/xmon/ppc-opc.c {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, RT 5362 arch/powerpc/xmon/ppc-opc.c {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, RT 5363 arch/powerpc/xmon/ppc-opc.c {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, RT 5364 arch/powerpc/xmon/ppc-opc.c {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, RT 5365 arch/powerpc/xmon/ppc-opc.c {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, RT 5366 arch/powerpc/xmon/ppc-opc.c {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, RT 5367 arch/powerpc/xmon/ppc-opc.c {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, RT 5368 arch/powerpc/xmon/ppc-opc.c {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, RT 5369 arch/powerpc/xmon/ppc-opc.c {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, RT 5370 arch/powerpc/xmon/ppc-opc.c {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, RT 5371 arch/powerpc/xmon/ppc-opc.c {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, RT 5372 arch/powerpc/xmon/ppc-opc.c {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, RT 5373 arch/powerpc/xmon/ppc-opc.c {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, RT 5374 arch/powerpc/xmon/ppc-opc.c {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, RT 5375 arch/powerpc/xmon/ppc-opc.c {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, RT 5376 arch/powerpc/xmon/ppc-opc.c {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, RT 5377 arch/powerpc/xmon/ppc-opc.c {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, RT 5378 arch/powerpc/xmon/ppc-opc.c {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, RT 5379 arch/powerpc/xmon/ppc-opc.c {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, RT 5380 arch/powerpc/xmon/ppc-opc.c {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, RT 5382 arch/powerpc/xmon/ppc-opc.c {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, RT 5383 arch/powerpc/xmon/ppc-opc.c {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, RT 5384 arch/powerpc/xmon/ppc-opc.c {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, RT 5385 arch/powerpc/xmon/ppc-opc.c {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, RT 5386 arch/powerpc/xmon/ppc-opc.c {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, RT 5387 arch/powerpc/xmon/ppc-opc.c {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, RT 5388 arch/powerpc/xmon/ppc-opc.c {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, RT 5389 arch/powerpc/xmon/ppc-opc.c {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, RT 5390 arch/powerpc/xmon/ppc-opc.c {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, RT 5391 arch/powerpc/xmon/ppc-opc.c {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, RT 5392 arch/powerpc/xmon/ppc-opc.c {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, RT 5393 arch/powerpc/xmon/ppc-opc.c {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, RT 5394 arch/powerpc/xmon/ppc-opc.c {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, RT 5395 arch/powerpc/xmon/ppc-opc.c {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, RT 5396 arch/powerpc/xmon/ppc-opc.c {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, RT 5397 arch/powerpc/xmon/ppc-opc.c {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, RT 5399 arch/powerpc/xmon/ppc-opc.c {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, RT 5403 arch/powerpc/xmon/ppc-opc.c {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, RT 5407 arch/powerpc/xmon/ppc-opc.c {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, RT 5408 arch/powerpc/xmon/ppc-opc.c {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, RT 5410 arch/powerpc/xmon/ppc-opc.c {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5411 arch/powerpc/xmon/ppc-opc.c {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5417 arch/powerpc/xmon/ppc-opc.c {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, RT 5418 arch/powerpc/xmon/ppc-opc.c {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, RT 5419 arch/powerpc/xmon/ppc-opc.c {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, RT 5421 arch/powerpc/xmon/ppc-opc.c {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, RT 5425 arch/powerpc/xmon/ppc-opc.c {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, RT 5437 arch/powerpc/xmon/ppc-opc.c {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5438 arch/powerpc/xmon/ppc-opc.c {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5439 arch/powerpc/xmon/ppc-opc.c {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5440 arch/powerpc/xmon/ppc-opc.c {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5469 arch/powerpc/xmon/ppc-opc.c {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5470 arch/powerpc/xmon/ppc-opc.c {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5471 arch/powerpc/xmon/ppc-opc.c {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5472 arch/powerpc/xmon/ppc-opc.c {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 5482 arch/powerpc/xmon/ppc-opc.c {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RT 5542 arch/powerpc/xmon/ppc-opc.c {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5543 arch/powerpc/xmon/ppc-opc.c {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5545 arch/powerpc/xmon/ppc-opc.c {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5546 arch/powerpc/xmon/ppc-opc.c {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5726 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, RT 5732 arch/powerpc/xmon/ppc-opc.c {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, RT 5733 arch/powerpc/xmon/ppc-opc.c {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, RT 5735 arch/powerpc/xmon/ppc-opc.c {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5736 arch/powerpc/xmon/ppc-opc.c {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5738 arch/powerpc/xmon/ppc-opc.c {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5739 arch/powerpc/xmon/ppc-opc.c {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5746 arch/powerpc/xmon/ppc-opc.c {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, RT 5754 arch/powerpc/xmon/ppc-opc.c {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, RT 5755 arch/powerpc/xmon/ppc-opc.c {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, RT 5762 arch/powerpc/xmon/ppc-opc.c {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5763 arch/powerpc/xmon/ppc-opc.c {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5764 arch/powerpc/xmon/ppc-opc.c {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RT 5765 arch/powerpc/xmon/ppc-opc.c {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5766 arch/powerpc/xmon/ppc-opc.c {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5767 arch/powerpc/xmon/ppc-opc.c {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RT 5769 arch/powerpc/xmon/ppc-opc.c {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5770 arch/powerpc/xmon/ppc-opc.c {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5771 arch/powerpc/xmon/ppc-opc.c {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5772 arch/powerpc/xmon/ppc-opc.c {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5776 arch/powerpc/xmon/ppc-opc.c {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, RT 5778 arch/powerpc/xmon/ppc-opc.c {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, RT 5780 arch/powerpc/xmon/ppc-opc.c {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, RT 5781 arch/powerpc/xmon/ppc-opc.c {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5783 arch/powerpc/xmon/ppc-opc.c {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RT 5784 arch/powerpc/xmon/ppc-opc.c {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5805 arch/powerpc/xmon/ppc-opc.c {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, RT 5806 arch/powerpc/xmon/ppc-opc.c {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, RT 5815 arch/powerpc/xmon/ppc-opc.c {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5816 arch/powerpc/xmon/ppc-opc.c {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RT 5817 arch/powerpc/xmon/ppc-opc.c {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 5818 arch/powerpc/xmon/ppc-opc.c {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RT 5829 arch/powerpc/xmon/ppc-opc.c {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, RT 5830 arch/powerpc/xmon/ppc-opc.c {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, RT 5834 arch/powerpc/xmon/ppc-opc.c {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, RT 5840 arch/powerpc/xmon/ppc-opc.c {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, RT 5842 arch/powerpc/xmon/ppc-opc.c {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, RT 5843 arch/powerpc/xmon/ppc-opc.c {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, RT 5860 arch/powerpc/xmon/ppc-opc.c {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, RT 5864 arch/powerpc/xmon/ppc-opc.c {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, RT 5868 arch/powerpc/xmon/ppc-opc.c {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, RT 5869 arch/powerpc/xmon/ppc-opc.c {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, RT 5871 arch/powerpc/xmon/ppc-opc.c {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5872 arch/powerpc/xmon/ppc-opc.c {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 5874 arch/powerpc/xmon/ppc-opc.c {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, RT 5890 arch/powerpc/xmon/ppc-opc.c {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5891 arch/powerpc/xmon/ppc-opc.c {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5892 arch/powerpc/xmon/ppc-opc.c {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5893 arch/powerpc/xmon/ppc-opc.c {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5895 arch/powerpc/xmon/ppc-opc.c {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5896 arch/powerpc/xmon/ppc-opc.c {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5897 arch/powerpc/xmon/ppc-opc.c {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5898 arch/powerpc/xmon/ppc-opc.c {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5900 arch/powerpc/xmon/ppc-opc.c {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, RT 5949 arch/powerpc/xmon/ppc-opc.c {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5950 arch/powerpc/xmon/ppc-opc.c {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5951 arch/powerpc/xmon/ppc-opc.c {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5952 arch/powerpc/xmon/ppc-opc.c {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5954 arch/powerpc/xmon/ppc-opc.c {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5955 arch/powerpc/xmon/ppc-opc.c {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5956 arch/powerpc/xmon/ppc-opc.c {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5957 arch/powerpc/xmon/ppc-opc.c {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5972 arch/powerpc/xmon/ppc-opc.c {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, RT 5983 arch/powerpc/xmon/ppc-opc.c {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5984 arch/powerpc/xmon/ppc-opc.c {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5985 arch/powerpc/xmon/ppc-opc.c {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5986 arch/powerpc/xmon/ppc-opc.c {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5988 arch/powerpc/xmon/ppc-opc.c {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5989 arch/powerpc/xmon/ppc-opc.c {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 5991 arch/powerpc/xmon/ppc-opc.c {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5992 arch/powerpc/xmon/ppc-opc.c {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5993 arch/powerpc/xmon/ppc-opc.c {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RT 5994 arch/powerpc/xmon/ppc-opc.c {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RT 5996 arch/powerpc/xmon/ppc-opc.c {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5997 arch/powerpc/xmon/ppc-opc.c {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 5998 arch/powerpc/xmon/ppc-opc.c {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 5999 arch/powerpc/xmon/ppc-opc.c {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 6005 arch/powerpc/xmon/ppc-opc.c {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, RT 6023 arch/powerpc/xmon/ppc-opc.c {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6024 arch/powerpc/xmon/ppc-opc.c {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6026 arch/powerpc/xmon/ppc-opc.c {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 6027 arch/powerpc/xmon/ppc-opc.c {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 6028 arch/powerpc/xmon/ppc-opc.c {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RT 6029 arch/powerpc/xmon/ppc-opc.c {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RT 6031 arch/powerpc/xmon/ppc-opc.c {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, RT 6032 arch/powerpc/xmon/ppc-opc.c {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, RT 6041 arch/powerpc/xmon/ppc-opc.c {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, RT 6043 arch/powerpc/xmon/ppc-opc.c {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, RT 6067 arch/powerpc/xmon/ppc-opc.c {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, RT 6071 arch/powerpc/xmon/ppc-opc.c {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, RT 6089 arch/powerpc/xmon/ppc-opc.c {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6090 arch/powerpc/xmon/ppc-opc.c {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6100 arch/powerpc/xmon/ppc-opc.c {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, RT 6101 arch/powerpc/xmon/ppc-opc.c {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, RT 6103 arch/powerpc/xmon/ppc-opc.c {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, RT 6114 arch/powerpc/xmon/ppc-opc.c {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, RT 6115 arch/powerpc/xmon/ppc-opc.c {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, RT 6117 arch/powerpc/xmon/ppc-opc.c {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6118 arch/powerpc/xmon/ppc-opc.c {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RT 6126 arch/powerpc/xmon/ppc-opc.c {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, RT 6140 arch/powerpc/xmon/ppc-opc.c {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6141 arch/powerpc/xmon/ppc-opc.c {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6142 arch/powerpc/xmon/ppc-opc.c {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6143 arch/powerpc/xmon/ppc-opc.c {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6153 arch/powerpc/xmon/ppc-opc.c {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, RT 6154 arch/powerpc/xmon/ppc-opc.c {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, RT 6184 arch/powerpc/xmon/ppc-opc.c {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6185 arch/powerpc/xmon/ppc-opc.c {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6186 arch/powerpc/xmon/ppc-opc.c {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6187 arch/powerpc/xmon/ppc-opc.c {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RT 6194 arch/powerpc/xmon/ppc-opc.c {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, RT 6195 arch/powerpc/xmon/ppc-opc.c {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, RT 6216 arch/powerpc/xmon/ppc-opc.c {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 6217 arch/powerpc/xmon/ppc-opc.c {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 6219 arch/powerpc/xmon/ppc-opc.c {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 6220 arch/powerpc/xmon/ppc-opc.c {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 6226 arch/powerpc/xmon/ppc-opc.c {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, RT 6227 arch/powerpc/xmon/ppc-opc.c {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, RT 6230 arch/powerpc/xmon/ppc-opc.c {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, RT 6247 arch/powerpc/xmon/ppc-opc.c {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, RT 6248 arch/powerpc/xmon/ppc-opc.c {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, RT 6250 arch/powerpc/xmon/ppc-opc.c {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 6251 arch/powerpc/xmon/ppc-opc.c {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RT 6253 arch/powerpc/xmon/ppc-opc.c {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 6254 arch/powerpc/xmon/ppc-opc.c {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RT 6284 arch/powerpc/xmon/ppc-opc.c {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, RT 6285 arch/powerpc/xmon/ppc-opc.c {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RT 6287 arch/powerpc/xmon/ppc-opc.c {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, RT 6288 arch/powerpc/xmon/ppc-opc.c {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RT 6290 arch/powerpc/xmon/ppc-opc.c {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RT 6292 arch/powerpc/xmon/ppc-opc.c {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, RT 6304 arch/powerpc/xmon/ppc-opc.c {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RT 6306 arch/powerpc/xmon/ppc-opc.c {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, RT 6308 arch/powerpc/xmon/ppc-opc.c {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RT 6310 arch/powerpc/xmon/ppc-opc.c {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, RT 6316 arch/powerpc/xmon/ppc-opc.c {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, RT 6317 arch/powerpc/xmon/ppc-opc.c {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RT 6348 arch/powerpc/xmon/ppc-opc.c {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, RT 6349 arch/powerpc/xmon/ppc-opc.c {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, RT 6350 arch/powerpc/xmon/ppc-opc.c {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, RT 6600 arch/powerpc/xmon/ppc-opc.c {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, RT 6601 arch/powerpc/xmon/ppc-opc.c {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, RT 7016 arch/powerpc/xmon/ppc-opc.c {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7017 arch/powerpc/xmon/ppc-opc.c {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RT 7018 arch/powerpc/xmon/ppc-opc.c {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7019 arch/powerpc/xmon/ppc-opc.c {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7020 arch/powerpc/xmon/ppc-opc.c {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RT 7021 arch/powerpc/xmon/ppc-opc.c {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7022 arch/powerpc/xmon/ppc-opc.c {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RT 7023 arch/powerpc/xmon/ppc-opc.c {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7024 arch/powerpc/xmon/ppc-opc.c {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7025 arch/powerpc/xmon/ppc-opc.c {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RT 7033 arch/powerpc/xmon/ppc-opc.c {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7034 arch/powerpc/xmon/ppc-opc.c {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7035 arch/powerpc/xmon/ppc-opc.c {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7036 arch/powerpc/xmon/ppc-opc.c {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7037 arch/powerpc/xmon/ppc-opc.c {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7038 arch/powerpc/xmon/ppc-opc.c {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7039 arch/powerpc/xmon/ppc-opc.c {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7040 arch/powerpc/xmon/ppc-opc.c {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7041 arch/powerpc/xmon/ppc-opc.c {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RT 7052 arch/powerpc/xmon/ppc-opc.c {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, RT 7053 arch/powerpc/xmon/ppc-opc.c {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7054 arch/powerpc/xmon/ppc-opc.c {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, RT 7064 arch/powerpc/xmon/ppc-opc.c {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7065 arch/powerpc/xmon/ppc-opc.c {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7066 arch/powerpc/xmon/ppc-opc.c {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7078 arch/powerpc/xmon/ppc-opc.c {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7079 arch/powerpc/xmon/ppc-opc.c {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7080 arch/powerpc/xmon/ppc-opc.c {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7081 arch/powerpc/xmon/ppc-opc.c {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RT 7105 arch/powerpc/xmon/ppc-opc.c {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, RT 7107 arch/powerpc/xmon/ppc-opc.c {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, RT 214 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); RT 92 drivers/media/platform/rockchip/rga/rga-hw.c LT, RT, LB, RB, RT 95 drivers/media/platform/rockchip/rga/rga-hw.c RT, LT, RB, LB, RT 98 drivers/media/platform/rockchip/rga/rga-hw.c RB, LB, RT, LT, RT 101 drivers/media/platform/rockchip/rga/rga-hw.c LB, RB, LT, RT, RT 113 drivers/media/platform/rockchip/rga/rga-hw.c case RT: RT 157 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) RT 158 drivers/pinctrl/pinctrl-st.c #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) RT 51 scripts/dtc/include-prefixes/arm/st-pincfg.h #define SE_NICLK_IO (RT) RT 56 scripts/dtc/include-prefixes/arm/st-pincfg.h #define SE_ICLK_IO (RT | INVERTCLK) RT 61 scripts/dtc/include-prefixes/arm/st-pincfg.h #define DE_IO (RT | DOUBLE_EDGE) RT 66 scripts/dtc/include-prefixes/arm/st-pincfg.h #define ICLK (RT | CLKNOTDATA | INVERTCLK) RT 71 scripts/dtc/include-prefixes/arm/st-pincfg.h #define NICLK (RT | CLKNOTDATA)