RS 43 arch/mips/mm/uasm-micromips.c [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD}, RS 44 arch/mips/mm/uasm-micromips.c [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 45 arch/mips/mm/uasm-micromips.c [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD}, RS 46 arch/mips/mm/uasm-micromips.c [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RS 47 arch/mips/mm/uasm-micromips.c [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 49 arch/mips/mm/uasm-micromips.c [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM}, RS 51 arch/mips/mm/uasm-micromips.c [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM}, RS 53 arch/mips/mm/uasm-micromips.c [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM}, RS 54 arch/mips/mm/uasm-micromips.c [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM}, RS 55 arch/mips/mm/uasm-micromips.c [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS}, RS 57 arch/mips/mm/uasm-micromips.c [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS}, RS 61 arch/mips/mm/uasm-micromips.c [insn_di] = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS}, RS 62 arch/mips/mm/uasm-micromips.c [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS}, RS 74 arch/mips/mm/uasm-micromips.c [insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE}, RS 75 arch/mips/mm/uasm-micromips.c [insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE}, RS 78 arch/mips/mm/uasm-micromips.c [insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS}, RS 79 arch/mips/mm/uasm-micromips.c [insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS}, RS 80 arch/mips/mm/uasm-micromips.c [insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 82 arch/mips/mm/uasm-micromips.c [insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 83 arch/mips/mm/uasm-micromips.c [insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM}, RS 85 arch/mips/mm/uasm-micromips.c [insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM}, RS 86 arch/mips/mm/uasm-micromips.c [insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 87 arch/mips/mm/uasm-micromips.c [insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD}, RS 88 arch/mips/mm/uasm-micromips.c [insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS}, RS 89 arch/mips/mm/uasm-micromips.c [insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS}, RS 90 arch/mips/mm/uasm-micromips.c [insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD}, RS 91 arch/mips/mm/uasm-micromips.c [insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS}, RS 92 arch/mips/mm/uasm-micromips.c [insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS}, RS 93 arch/mips/mm/uasm-micromips.c [insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD}, RS 94 arch/mips/mm/uasm-micromips.c [insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD}, RS 95 arch/mips/mm/uasm-micromips.c [insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RS 96 arch/mips/mm/uasm-micromips.c [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM}, RS 98 arch/mips/mm/uasm-micromips.c [insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM}, RS 101 arch/mips/mm/uasm-micromips.c [insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD}, RS 102 arch/mips/mm/uasm-micromips.c [insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD}, RS 103 arch/mips/mm/uasm-micromips.c [insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD}, RS 104 arch/mips/mm/uasm-micromips.c [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 105 arch/mips/mm/uasm-micromips.c [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD}, RS 106 arch/mips/mm/uasm-micromips.c [insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD}, RS 107 arch/mips/mm/uasm-micromips.c [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD}, RS 108 arch/mips/mm/uasm-micromips.c [insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD}, RS 109 arch/mips/mm/uasm-micromips.c [insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD}, RS 110 arch/mips/mm/uasm-micromips.c [insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD}, RS 111 arch/mips/mm/uasm-micromips.c [insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD}, RS 112 arch/mips/mm/uasm-micromips.c [insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, RS 113 arch/mips/mm/uasm-micromips.c [insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS}, RS 119 arch/mips/mm/uasm-micromips.c [insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS}, RS 120 arch/mips/mm/uasm-micromips.c [insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD}, RS 121 arch/mips/mm/uasm-micromips.c [insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, RS 171 arch/mips/mm/uasm-micromips.c if (ip->fields & RS) { RS 51 arch/mips/mm/uasm-mips.c [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 52 arch/mips/mm/uasm-mips.c [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, RS 53 arch/mips/mm/uasm-mips.c [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, RS 54 arch/mips/mm/uasm-mips.c [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RS 55 arch/mips/mm/uasm-mips.c [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 56 arch/mips/mm/uasm-mips.c [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 57 arch/mips/mm/uasm-mips.c [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 58 arch/mips/mm/uasm-mips.c [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 59 arch/mips/mm/uasm-mips.c [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, RS 60 arch/mips/mm/uasm-mips.c [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM}, RS 61 arch/mips/mm/uasm-mips.c [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM}, RS 62 arch/mips/mm/uasm-mips.c [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM}, RS 63 arch/mips/mm/uasm-mips.c [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM}, RS 64 arch/mips/mm/uasm-mips.c [insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM}, RS 65 arch/mips/mm/uasm-mips.c [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, RS 68 arch/mips/mm/uasm-mips.c [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 70 arch/mips/mm/uasm-mips.c [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, RS 76 arch/mips/mm/uasm-mips.c [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 77 arch/mips/mm/uasm-mips.c [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, RS 78 arch/mips/mm/uasm-mips.c [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, RS 80 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 82 arch/mips/mm/uasm-mips.c [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, RS 83 arch/mips/mm/uasm-mips.c [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, RS 84 arch/mips/mm/uasm-mips.c [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, RS 85 arch/mips/mm/uasm-mips.c [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, RS 87 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 90 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 92 arch/mips/mm/uasm-mips.c [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, RS 94 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 101 arch/mips/mm/uasm-mips.c [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD}, RS 104 arch/mips/mm/uasm-mips.c [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD}, RS 107 arch/mips/mm/uasm-mips.c [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD}, RS 108 arch/mips/mm/uasm-mips.c [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD}, RS 110 arch/mips/mm/uasm-mips.c [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE}, RS 111 arch/mips/mm/uasm-mips.c [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE}, RS 114 arch/mips/mm/uasm-mips.c [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD}, RS 116 arch/mips/mm/uasm-mips.c [insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS}, RS 118 arch/mips/mm/uasm-mips.c [insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS}, RS 120 arch/mips/mm/uasm-mips.c [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 121 arch/mips/mm/uasm-mips.c [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 122 arch/mips/mm/uasm-mips.c [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 123 arch/mips/mm/uasm-mips.c [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD}, RS 124 arch/mips/mm/uasm-mips.c [insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD}, RS 125 arch/mips/mm/uasm-mips.c [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD}, RS 126 arch/mips/mm/uasm-mips.c [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 127 arch/mips/mm/uasm-mips.c [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 129 arch/mips/mm/uasm-mips.c [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 130 arch/mips/mm/uasm-mips.c [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 132 arch/mips/mm/uasm-mips.c [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, RS 133 arch/mips/mm/uasm-mips.c [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, RS 136 arch/mips/mm/uasm-mips.c [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 137 arch/mips/mm/uasm-mips.c [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 138 arch/mips/mm/uasm-mips.c [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD}, RS 144 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 145 arch/mips/mm/uasm-mips.c [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, RS 146 arch/mips/mm/uasm-mips.c [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD}, RS 149 arch/mips/mm/uasm-mips.c [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS}, RS 150 arch/mips/mm/uasm-mips.c [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, RS 152 arch/mips/mm/uasm-mips.c RS | RT | RD}, RS 154 arch/mips/mm/uasm-mips.c [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, RS 156 arch/mips/mm/uasm-mips.c [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD}, RS 158 arch/mips/mm/uasm-mips.c [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT}, RS 159 arch/mips/mm/uasm-mips.c [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD}, RS 160 arch/mips/mm/uasm-mips.c [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD}, RS 161 arch/mips/mm/uasm-mips.c [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RS 163 arch/mips/mm/uasm-mips.c [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 165 arch/mips/mm/uasm-mips.c [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, RS 169 arch/mips/mm/uasm-mips.c [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 171 arch/mips/mm/uasm-mips.c [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 172 arch/mips/mm/uasm-mips.c [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 174 arch/mips/mm/uasm-mips.c [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, RS 175 arch/mips/mm/uasm-mips.c [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9}, RS 177 arch/mips/mm/uasm-mips.c [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 178 arch/mips/mm/uasm-mips.c [insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD}, RS 179 arch/mips/mm/uasm-mips.c [insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD}, RS 180 arch/mips/mm/uasm-mips.c [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 182 arch/mips/mm/uasm-mips.c [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD}, RS 183 arch/mips/mm/uasm-mips.c [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD}, RS 184 arch/mips/mm/uasm-mips.c [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 185 arch/mips/mm/uasm-mips.c [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 186 arch/mips/mm/uasm-mips.c [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, RS 188 arch/mips/mm/uasm-mips.c [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD}, RS 190 arch/mips/mm/uasm-mips.c [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, RS 191 arch/mips/mm/uasm-mips.c [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD}, RS 192 arch/mips/mm/uasm-mips.c [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, RS 201 arch/mips/mm/uasm-mips.c [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD}, RS 202 arch/mips/mm/uasm-mips.c [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, RS 203 arch/mips/mm/uasm-mips.c [insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD}, RS 245 arch/mips/mm/uasm-mips.c if (ip->fields & RS) RS 23 arch/powerpc/include/asm/asm-compat.h #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS) RS 422 arch/powerpc/include/asm/ppc_asm.h #define MTOCRF(FXM, RS) \ RS 424 arch/powerpc/include/asm/ppc_asm.h mtcrf (FXM), RS; \ RS 426 arch/powerpc/include/asm/ppc_asm.h mtocrf (FXM), RS; \ RS 54 arch/powerpc/platforms/powermac/time.c #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ RS 55 arch/powerpc/platforms/powermac/time.c #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ RS 56 arch/powerpc/platforms/powermac/time.c #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ RS 57 arch/powerpc/platforms/powermac/time.c #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ RS 58 arch/powerpc/platforms/powermac/time.c #define ACR (11*RS) /* Auxiliary control register */ RS 59 arch/powerpc/platforms/powermac/time.c #define IFR (13*RS) /* Interrupt flag register */ RS 566 arch/powerpc/xmon/ppc-opc.c #define RT RS RS 568 arch/powerpc/xmon/ppc-opc.c #define RD RS RS 573 arch/powerpc/xmon/ppc-opc.c #define RSQ RS + 1 RS 3260 arch/powerpc/xmon/ppc-opc.c {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3263 arch/powerpc/xmon/ppc-opc.c {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, RS 3265 arch/powerpc/xmon/ppc-opc.c {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3266 arch/powerpc/xmon/ppc-opc.c {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, RS 3268 arch/powerpc/xmon/ppc-opc.c {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, RS 3269 arch/powerpc/xmon/ppc-opc.c {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, RS 3271 arch/powerpc/xmon/ppc-opc.c {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3273 arch/powerpc/xmon/ppc-opc.c {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3274 arch/powerpc/xmon/ppc-opc.c {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3276 arch/powerpc/xmon/ppc-opc.c {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3277 arch/powerpc/xmon/ppc-opc.c {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3280 arch/powerpc/xmon/ppc-opc.c {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3281 arch/powerpc/xmon/ppc-opc.c {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3283 arch/powerpc/xmon/ppc-opc.c {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3286 arch/powerpc/xmon/ppc-opc.c {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3287 arch/powerpc/xmon/ppc-opc.c {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3288 arch/powerpc/xmon/ppc-opc.c {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3289 arch/powerpc/xmon/ppc-opc.c {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, RS 3290 arch/powerpc/xmon/ppc-opc.c {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3291 arch/powerpc/xmon/ppc-opc.c {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3292 arch/powerpc/xmon/ppc-opc.c {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, RS 3294 arch/powerpc/xmon/ppc-opc.c {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3295 arch/powerpc/xmon/ppc-opc.c {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3296 arch/powerpc/xmon/ppc-opc.c {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3297 arch/powerpc/xmon/ppc-opc.c {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3298 arch/powerpc/xmon/ppc-opc.c {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3299 arch/powerpc/xmon/ppc-opc.c {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RS 3300 arch/powerpc/xmon/ppc-opc.c {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RS 3301 arch/powerpc/xmon/ppc-opc.c {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3302 arch/powerpc/xmon/ppc-opc.c {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RS 3303 arch/powerpc/xmon/ppc-opc.c {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3304 arch/powerpc/xmon/ppc-opc.c {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, RS 3305 arch/powerpc/xmon/ppc-opc.c {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RS 3306 arch/powerpc/xmon/ppc-opc.c {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, RS 3307 arch/powerpc/xmon/ppc-opc.c {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3308 arch/powerpc/xmon/ppc-opc.c {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3309 arch/powerpc/xmon/ppc-opc.c {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3310 arch/powerpc/xmon/ppc-opc.c {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3328 arch/powerpc/xmon/ppc-opc.c {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, RS 3330 arch/powerpc/xmon/ppc-opc.c {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3332 arch/powerpc/xmon/ppc-opc.c {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3334 arch/powerpc/xmon/ppc-opc.c {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3336 arch/powerpc/xmon/ppc-opc.c {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3337 arch/powerpc/xmon/ppc-opc.c {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3340 arch/powerpc/xmon/ppc-opc.c {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3341 arch/powerpc/xmon/ppc-opc.c {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3349 arch/powerpc/xmon/ppc-opc.c {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3350 arch/powerpc/xmon/ppc-opc.c {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3351 arch/powerpc/xmon/ppc-opc.c {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3352 arch/powerpc/xmon/ppc-opc.c {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3353 arch/powerpc/xmon/ppc-opc.c {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3354 arch/powerpc/xmon/ppc-opc.c {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3355 arch/powerpc/xmon/ppc-opc.c {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3356 arch/powerpc/xmon/ppc-opc.c {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3357 arch/powerpc/xmon/ppc-opc.c {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3359 arch/powerpc/xmon/ppc-opc.c {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, RS 3364 arch/powerpc/xmon/ppc-opc.c {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3365 arch/powerpc/xmon/ppc-opc.c {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3367 arch/powerpc/xmon/ppc-opc.c {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3369 arch/powerpc/xmon/ppc-opc.c {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3370 arch/powerpc/xmon/ppc-opc.c {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3373 arch/powerpc/xmon/ppc-opc.c {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3374 arch/powerpc/xmon/ppc-opc.c {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3381 arch/powerpc/xmon/ppc-opc.c {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3382 arch/powerpc/xmon/ppc-opc.c {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3383 arch/powerpc/xmon/ppc-opc.c {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3384 arch/powerpc/xmon/ppc-opc.c {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3385 arch/powerpc/xmon/ppc-opc.c {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3386 arch/powerpc/xmon/ppc-opc.c {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3387 arch/powerpc/xmon/ppc-opc.c {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3388 arch/powerpc/xmon/ppc-opc.c {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3389 arch/powerpc/xmon/ppc-opc.c {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3390 arch/powerpc/xmon/ppc-opc.c {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3392 arch/powerpc/xmon/ppc-opc.c {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3396 arch/powerpc/xmon/ppc-opc.c {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3397 arch/powerpc/xmon/ppc-opc.c {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3398 arch/powerpc/xmon/ppc-opc.c {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3399 arch/powerpc/xmon/ppc-opc.c {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3400 arch/powerpc/xmon/ppc-opc.c {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3401 arch/powerpc/xmon/ppc-opc.c {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3402 arch/powerpc/xmon/ppc-opc.c {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, RS 3403 arch/powerpc/xmon/ppc-opc.c {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3404 arch/powerpc/xmon/ppc-opc.c {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RS 3405 arch/powerpc/xmon/ppc-opc.c {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3406 arch/powerpc/xmon/ppc-opc.c {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3410 arch/powerpc/xmon/ppc-opc.c {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3411 arch/powerpc/xmon/ppc-opc.c {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3412 arch/powerpc/xmon/ppc-opc.c {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3413 arch/powerpc/xmon/ppc-opc.c {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3414 arch/powerpc/xmon/ppc-opc.c {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3415 arch/powerpc/xmon/ppc-opc.c {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3416 arch/powerpc/xmon/ppc-opc.c {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3417 arch/powerpc/xmon/ppc-opc.c {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3418 arch/powerpc/xmon/ppc-opc.c {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3419 arch/powerpc/xmon/ppc-opc.c {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3421 arch/powerpc/xmon/ppc-opc.c {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, RS 3425 arch/powerpc/xmon/ppc-opc.c {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3427 arch/powerpc/xmon/ppc-opc.c {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3428 arch/powerpc/xmon/ppc-opc.c {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3430 arch/powerpc/xmon/ppc-opc.c {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3431 arch/powerpc/xmon/ppc-opc.c {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3433 arch/powerpc/xmon/ppc-opc.c {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3435 arch/powerpc/xmon/ppc-opc.c {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3437 arch/powerpc/xmon/ppc-opc.c {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RS 3440 arch/powerpc/xmon/ppc-opc.c {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3443 arch/powerpc/xmon/ppc-opc.c {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RS 3444 arch/powerpc/xmon/ppc-opc.c {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3446 arch/powerpc/xmon/ppc-opc.c {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RS 3448 arch/powerpc/xmon/ppc-opc.c {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3450 arch/powerpc/xmon/ppc-opc.c {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3451 arch/powerpc/xmon/ppc-opc.c {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3452 arch/powerpc/xmon/ppc-opc.c {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3453 arch/powerpc/xmon/ppc-opc.c {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3454 arch/powerpc/xmon/ppc-opc.c {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3456 arch/powerpc/xmon/ppc-opc.c {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3458 arch/powerpc/xmon/ppc-opc.c {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3459 arch/powerpc/xmon/ppc-opc.c {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3460 arch/powerpc/xmon/ppc-opc.c {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3461 arch/powerpc/xmon/ppc-opc.c {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3462 arch/powerpc/xmon/ppc-opc.c {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3463 arch/powerpc/xmon/ppc-opc.c {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3464 arch/powerpc/xmon/ppc-opc.c {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3465 arch/powerpc/xmon/ppc-opc.c {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3466 arch/powerpc/xmon/ppc-opc.c {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RS 3467 arch/powerpc/xmon/ppc-opc.c {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3468 arch/powerpc/xmon/ppc-opc.c {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3469 arch/powerpc/xmon/ppc-opc.c {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3470 arch/powerpc/xmon/ppc-opc.c {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3471 arch/powerpc/xmon/ppc-opc.c {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3472 arch/powerpc/xmon/ppc-opc.c {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3473 arch/powerpc/xmon/ppc-opc.c {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3474 arch/powerpc/xmon/ppc-opc.c {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RS 3519 arch/powerpc/xmon/ppc-opc.c {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3525 arch/powerpc/xmon/ppc-opc.c {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3527 arch/powerpc/xmon/ppc-opc.c {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3528 arch/powerpc/xmon/ppc-opc.c {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3530 arch/powerpc/xmon/ppc-opc.c {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3531 arch/powerpc/xmon/ppc-opc.c {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3533 arch/powerpc/xmon/ppc-opc.c {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3534 arch/powerpc/xmon/ppc-opc.c {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3539 arch/powerpc/xmon/ppc-opc.c {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3540 arch/powerpc/xmon/ppc-opc.c {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3541 arch/powerpc/xmon/ppc-opc.c {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3542 arch/powerpc/xmon/ppc-opc.c {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3543 arch/powerpc/xmon/ppc-opc.c {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3544 arch/powerpc/xmon/ppc-opc.c {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3545 arch/powerpc/xmon/ppc-opc.c {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3546 arch/powerpc/xmon/ppc-opc.c {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3556 arch/powerpc/xmon/ppc-opc.c {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3558 arch/powerpc/xmon/ppc-opc.c {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3560 arch/powerpc/xmon/ppc-opc.c {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3562 arch/powerpc/xmon/ppc-opc.c {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3564 arch/powerpc/xmon/ppc-opc.c {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3565 arch/powerpc/xmon/ppc-opc.c {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3567 arch/powerpc/xmon/ppc-opc.c {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3569 arch/powerpc/xmon/ppc-opc.c {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3570 arch/powerpc/xmon/ppc-opc.c {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3575 arch/powerpc/xmon/ppc-opc.c {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3576 arch/powerpc/xmon/ppc-opc.c {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3577 arch/powerpc/xmon/ppc-opc.c {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3578 arch/powerpc/xmon/ppc-opc.c {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3579 arch/powerpc/xmon/ppc-opc.c {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3580 arch/powerpc/xmon/ppc-opc.c {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3581 arch/powerpc/xmon/ppc-opc.c {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3582 arch/powerpc/xmon/ppc-opc.c {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3583 arch/powerpc/xmon/ppc-opc.c {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3600 arch/powerpc/xmon/ppc-opc.c {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3602 arch/powerpc/xmon/ppc-opc.c {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3603 arch/powerpc/xmon/ppc-opc.c {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3604 arch/powerpc/xmon/ppc-opc.c {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3605 arch/powerpc/xmon/ppc-opc.c {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3607 arch/powerpc/xmon/ppc-opc.c {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3612 arch/powerpc/xmon/ppc-opc.c {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3614 arch/powerpc/xmon/ppc-opc.c {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3615 arch/powerpc/xmon/ppc-opc.c {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3616 arch/powerpc/xmon/ppc-opc.c {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3617 arch/powerpc/xmon/ppc-opc.c {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, RS 3626 arch/powerpc/xmon/ppc-opc.c {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3628 arch/powerpc/xmon/ppc-opc.c {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3630 arch/powerpc/xmon/ppc-opc.c {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3631 arch/powerpc/xmon/ppc-opc.c {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3634 arch/powerpc/xmon/ppc-opc.c {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3638 arch/powerpc/xmon/ppc-opc.c {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3639 arch/powerpc/xmon/ppc-opc.c {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3642 arch/powerpc/xmon/ppc-opc.c {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3643 arch/powerpc/xmon/ppc-opc.c {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3645 arch/powerpc/xmon/ppc-opc.c {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3646 arch/powerpc/xmon/ppc-opc.c {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3647 arch/powerpc/xmon/ppc-opc.c {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3650 arch/powerpc/xmon/ppc-opc.c {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3651 arch/powerpc/xmon/ppc-opc.c {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3652 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3653 arch/powerpc/xmon/ppc-opc.c {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3654 arch/powerpc/xmon/ppc-opc.c {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3655 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3657 arch/powerpc/xmon/ppc-opc.c {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3659 arch/powerpc/xmon/ppc-opc.c {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3666 arch/powerpc/xmon/ppc-opc.c {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3668 arch/powerpc/xmon/ppc-opc.c {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3671 arch/powerpc/xmon/ppc-opc.c {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3673 arch/powerpc/xmon/ppc-opc.c {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3675 arch/powerpc/xmon/ppc-opc.c {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3676 arch/powerpc/xmon/ppc-opc.c {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3679 arch/powerpc/xmon/ppc-opc.c {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3681 arch/powerpc/xmon/ppc-opc.c {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3690 arch/powerpc/xmon/ppc-opc.c {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3692 arch/powerpc/xmon/ppc-opc.c {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3693 arch/powerpc/xmon/ppc-opc.c {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3697 arch/powerpc/xmon/ppc-opc.c {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3698 arch/powerpc/xmon/ppc-opc.c {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3699 arch/powerpc/xmon/ppc-opc.c {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3700 arch/powerpc/xmon/ppc-opc.c {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3701 arch/powerpc/xmon/ppc-opc.c {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3702 arch/powerpc/xmon/ppc-opc.c {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3703 arch/powerpc/xmon/ppc-opc.c {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3706 arch/powerpc/xmon/ppc-opc.c {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3707 arch/powerpc/xmon/ppc-opc.c {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3708 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3709 arch/powerpc/xmon/ppc-opc.c {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3710 arch/powerpc/xmon/ppc-opc.c {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3711 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3712 arch/powerpc/xmon/ppc-opc.c {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3714 arch/powerpc/xmon/ppc-opc.c {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3720 arch/powerpc/xmon/ppc-opc.c {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3721 arch/powerpc/xmon/ppc-opc.c {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3724 arch/powerpc/xmon/ppc-opc.c {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3726 arch/powerpc/xmon/ppc-opc.c {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3728 arch/powerpc/xmon/ppc-opc.c {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 3729 arch/powerpc/xmon/ppc-opc.c {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RS 4587 arch/powerpc/xmon/ppc-opc.c {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4588 arch/powerpc/xmon/ppc-opc.c {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4590 arch/powerpc/xmon/ppc-opc.c {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4591 arch/powerpc/xmon/ppc-opc.c {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4593 arch/powerpc/xmon/ppc-opc.c {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, RS 4594 arch/powerpc/xmon/ppc-opc.c {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, RS 4595 arch/powerpc/xmon/ppc-opc.c {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4596 arch/powerpc/xmon/ppc-opc.c {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4597 arch/powerpc/xmon/ppc-opc.c {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, RS 4598 arch/powerpc/xmon/ppc-opc.c {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, RS 4599 arch/powerpc/xmon/ppc-opc.c {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4600 arch/powerpc/xmon/ppc-opc.c {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RS 4602 arch/powerpc/xmon/ppc-opc.c {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4603 arch/powerpc/xmon/ppc-opc.c {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4605 arch/powerpc/xmon/ppc-opc.c {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RS 4606 arch/powerpc/xmon/ppc-opc.c {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4607 arch/powerpc/xmon/ppc-opc.c {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4608 arch/powerpc/xmon/ppc-opc.c {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RS 4609 arch/powerpc/xmon/ppc-opc.c {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4610 arch/powerpc/xmon/ppc-opc.c {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RS 4613 arch/powerpc/xmon/ppc-opc.c {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4614 arch/powerpc/xmon/ppc-opc.c {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4616 arch/powerpc/xmon/ppc-opc.c {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4617 arch/powerpc/xmon/ppc-opc.c {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4620 arch/powerpc/xmon/ppc-opc.c {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4621 arch/powerpc/xmon/ppc-opc.c {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4623 arch/powerpc/xmon/ppc-opc.c {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4624 arch/powerpc/xmon/ppc-opc.c {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4626 arch/powerpc/xmon/ppc-opc.c {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4627 arch/powerpc/xmon/ppc-opc.c {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4629 arch/powerpc/xmon/ppc-opc.c {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RS 4630 arch/powerpc/xmon/ppc-opc.c {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RS 4632 arch/powerpc/xmon/ppc-opc.c {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, RS 4633 arch/powerpc/xmon/ppc-opc.c {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, RS 4634 arch/powerpc/xmon/ppc-opc.c {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4635 arch/powerpc/xmon/ppc-opc.c {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, RS 4636 arch/powerpc/xmon/ppc-opc.c {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, RS 4637 arch/powerpc/xmon/ppc-opc.c {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4639 arch/powerpc/xmon/ppc-opc.c {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, RS 4640 arch/powerpc/xmon/ppc-opc.c {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, RS 4642 arch/powerpc/xmon/ppc-opc.c {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4643 arch/powerpc/xmon/ppc-opc.c {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4645 arch/powerpc/xmon/ppc-opc.c {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4646 arch/powerpc/xmon/ppc-opc.c {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RS 4648 arch/powerpc/xmon/ppc-opc.c {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RS 4649 arch/powerpc/xmon/ppc-opc.c {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RS 4650 arch/powerpc/xmon/ppc-opc.c {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RS 4651 arch/powerpc/xmon/ppc-opc.c {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RS 4653 arch/powerpc/xmon/ppc-opc.c {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RS 4654 arch/powerpc/xmon/ppc-opc.c {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RS 4738 arch/powerpc/xmon/ppc-opc.c {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 4739 arch/powerpc/xmon/ppc-opc.c {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 4740 arch/powerpc/xmon/ppc-opc.c {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 4741 arch/powerpc/xmon/ppc-opc.c {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 4743 arch/powerpc/xmon/ppc-opc.c {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, RS 4744 arch/powerpc/xmon/ppc-opc.c {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, RS 4745 arch/powerpc/xmon/ppc-opc.c {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, RS 4746 arch/powerpc/xmon/ppc-opc.c {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, RS 4748 arch/powerpc/xmon/ppc-opc.c {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 4749 arch/powerpc/xmon/ppc-opc.c {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 4751 arch/powerpc/xmon/ppc-opc.c {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 4752 arch/powerpc/xmon/ppc-opc.c {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 4754 arch/powerpc/xmon/ppc-opc.c {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, RS 4755 arch/powerpc/xmon/ppc-opc.c {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, RS 4806 arch/powerpc/xmon/ppc-opc.c {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, RS 4807 arch/powerpc/xmon/ppc-opc.c {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, RS 4809 arch/powerpc/xmon/ppc-opc.c {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 4810 arch/powerpc/xmon/ppc-opc.c {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 4842 arch/powerpc/xmon/ppc-opc.c {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RS 4843 arch/powerpc/xmon/ppc-opc.c {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RS 4845 arch/powerpc/xmon/ppc-opc.c {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, RS 4871 arch/powerpc/xmon/ppc-opc.c {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, RS 4883 arch/powerpc/xmon/ppc-opc.c {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, RS 4885 arch/powerpc/xmon/ppc-opc.c {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}}, RS 4886 arch/powerpc/xmon/ppc-opc.c {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 4887 arch/powerpc/xmon/ppc-opc.c {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}}, RS 4888 arch/powerpc/xmon/ppc-opc.c {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 4894 arch/powerpc/xmon/ppc-opc.c {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, RS 4916 arch/powerpc/xmon/ppc-opc.c {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, RS 4917 arch/powerpc/xmon/ppc-opc.c {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, RS 4918 arch/powerpc/xmon/ppc-opc.c {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, RS 4920 arch/powerpc/xmon/ppc-opc.c {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, RS 4927 arch/powerpc/xmon/ppc-opc.c {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, RS 4929 arch/powerpc/xmon/ppc-opc.c {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, RS 4931 arch/powerpc/xmon/ppc-opc.c {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RS 4932 arch/powerpc/xmon/ppc-opc.c {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, RS 4934 arch/powerpc/xmon/ppc-opc.c {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 4935 arch/powerpc/xmon/ppc-opc.c {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 4937 arch/powerpc/xmon/ppc-opc.c {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 4938 arch/powerpc/xmon/ppc-opc.c {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 4940 arch/powerpc/xmon/ppc-opc.c {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, RS 4942 arch/powerpc/xmon/ppc-opc.c {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RS 4944 arch/powerpc/xmon/ppc-opc.c {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RS 4958 arch/powerpc/xmon/ppc-opc.c {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, RS 4965 arch/powerpc/xmon/ppc-opc.c {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, RS 4970 arch/powerpc/xmon/ppc-opc.c {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, RS 4971 arch/powerpc/xmon/ppc-opc.c {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RS 4973 arch/powerpc/xmon/ppc-opc.c {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, RS 4974 arch/powerpc/xmon/ppc-opc.c {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, RS 4976 arch/powerpc/xmon/ppc-opc.c {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, RS 4997 arch/powerpc/xmon/ppc-opc.c {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, RS 5002 arch/powerpc/xmon/ppc-opc.c {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, RS 5006 arch/powerpc/xmon/ppc-opc.c {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, RS 5008 arch/powerpc/xmon/ppc-opc.c {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, RS 5010 arch/powerpc/xmon/ppc-opc.c {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5011 arch/powerpc/xmon/ppc-opc.c {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5013 arch/powerpc/xmon/ppc-opc.c {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5014 arch/powerpc/xmon/ppc-opc.c {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5016 arch/powerpc/xmon/ppc-opc.c {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RS 5045 arch/powerpc/xmon/ppc-opc.c {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, RS 5046 arch/powerpc/xmon/ppc-opc.c {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, RS 5057 arch/powerpc/xmon/ppc-opc.c {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, RS 5059 arch/powerpc/xmon/ppc-opc.c {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, RS 5060 arch/powerpc/xmon/ppc-opc.c {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, RS 5062 arch/powerpc/xmon/ppc-opc.c {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, RS 5066 arch/powerpc/xmon/ppc-opc.c {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, RS 5067 arch/powerpc/xmon/ppc-opc.c {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, RS 5110 arch/powerpc/xmon/ppc-opc.c {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, RS 5112 arch/powerpc/xmon/ppc-opc.c {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 5113 arch/powerpc/xmon/ppc-opc.c {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 5117 arch/powerpc/xmon/ppc-opc.c {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}}, RS 5126 arch/powerpc/xmon/ppc-opc.c {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, RS 5127 arch/powerpc/xmon/ppc-opc.c {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, RS 5139 arch/powerpc/xmon/ppc-opc.c {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, RS 5141 arch/powerpc/xmon/ppc-opc.c {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 5142 arch/powerpc/xmon/ppc-opc.c {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 5381 arch/powerpc/xmon/ppc-opc.c {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, RS 5427 arch/powerpc/xmon/ppc-opc.c {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, RS 5429 arch/powerpc/xmon/ppc-opc.c {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, RS 5430 arch/powerpc/xmon/ppc-opc.c {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, RS 5447 arch/powerpc/xmon/ppc-opc.c {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, RS 5451 arch/powerpc/xmon/ppc-opc.c {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, RS 5453 arch/powerpc/xmon/ppc-opc.c {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RS 5454 arch/powerpc/xmon/ppc-opc.c {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RS 5456 arch/powerpc/xmon/ppc-opc.c {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, RS 5458 arch/powerpc/xmon/ppc-opc.c {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 5459 arch/powerpc/xmon/ppc-opc.c {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 5461 arch/powerpc/xmon/ppc-opc.c {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RS 5463 arch/powerpc/xmon/ppc-opc.c {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}}, RS 5484 arch/powerpc/xmon/ppc-opc.c {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, RS 5495 arch/powerpc/xmon/ppc-opc.c {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}}, RS 5496 arch/powerpc/xmon/ppc-opc.c {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 5497 arch/powerpc/xmon/ppc-opc.c {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}}, RS 5498 arch/powerpc/xmon/ppc-opc.c {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 5500 arch/powerpc/xmon/ppc-opc.c {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, RS 5501 arch/powerpc/xmon/ppc-opc.c {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, RS 5502 arch/powerpc/xmon/ppc-opc.c {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, RS 5503 arch/powerpc/xmon/ppc-opc.c {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, RS 5504 arch/powerpc/xmon/ppc-opc.c {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, RS 5505 arch/powerpc/xmon/ppc-opc.c {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, RS 5506 arch/powerpc/xmon/ppc-opc.c {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, RS 5507 arch/powerpc/xmon/ppc-opc.c {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, RS 5508 arch/powerpc/xmon/ppc-opc.c {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, RS 5509 arch/powerpc/xmon/ppc-opc.c {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, RS 5510 arch/powerpc/xmon/ppc-opc.c {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, RS 5511 arch/powerpc/xmon/ppc-opc.c {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, RS 5512 arch/powerpc/xmon/ppc-opc.c {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, RS 5513 arch/powerpc/xmon/ppc-opc.c {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, RS 5514 arch/powerpc/xmon/ppc-opc.c {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, RS 5515 arch/powerpc/xmon/ppc-opc.c {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, RS 5516 arch/powerpc/xmon/ppc-opc.c {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, RS 5517 arch/powerpc/xmon/ppc-opc.c {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, RS 5518 arch/powerpc/xmon/ppc-opc.c {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, RS 5519 arch/powerpc/xmon/ppc-opc.c {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, RS 5520 arch/powerpc/xmon/ppc-opc.c {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, RS 5521 arch/powerpc/xmon/ppc-opc.c {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, RS 5522 arch/powerpc/xmon/ppc-opc.c {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, RS 5523 arch/powerpc/xmon/ppc-opc.c {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, RS 5524 arch/powerpc/xmon/ppc-opc.c {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, RS 5525 arch/powerpc/xmon/ppc-opc.c {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, RS 5526 arch/powerpc/xmon/ppc-opc.c {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, RS 5527 arch/powerpc/xmon/ppc-opc.c {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, RS 5528 arch/powerpc/xmon/ppc-opc.c {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, RS 5529 arch/powerpc/xmon/ppc-opc.c {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, RS 5530 arch/powerpc/xmon/ppc-opc.c {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, RS 5531 arch/powerpc/xmon/ppc-opc.c {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, RS 5532 arch/powerpc/xmon/ppc-opc.c {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, RS 5533 arch/powerpc/xmon/ppc-opc.c {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, RS 5534 arch/powerpc/xmon/ppc-opc.c {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, RS 5535 arch/powerpc/xmon/ppc-opc.c {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, RS 5548 arch/powerpc/xmon/ppc-opc.c {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, RS 5549 arch/powerpc/xmon/ppc-opc.c {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}}, RS 5551 arch/powerpc/xmon/ppc-opc.c {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, RS 5553 arch/powerpc/xmon/ppc-opc.c {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, RS 5554 arch/powerpc/xmon/ppc-opc.c {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, RS 5555 arch/powerpc/xmon/ppc-opc.c {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, RS 5556 arch/powerpc/xmon/ppc-opc.c {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, RS 5557 arch/powerpc/xmon/ppc-opc.c {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, RS 5558 arch/powerpc/xmon/ppc-opc.c {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, RS 5559 arch/powerpc/xmon/ppc-opc.c {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, RS 5560 arch/powerpc/xmon/ppc-opc.c {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, RS 5561 arch/powerpc/xmon/ppc-opc.c {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, RS 5562 arch/powerpc/xmon/ppc-opc.c {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, RS 5563 arch/powerpc/xmon/ppc-opc.c {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, RS 5564 arch/powerpc/xmon/ppc-opc.c {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, RS 5565 arch/powerpc/xmon/ppc-opc.c {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, RS 5566 arch/powerpc/xmon/ppc-opc.c {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, RS 5567 arch/powerpc/xmon/ppc-opc.c {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, RS 5568 arch/powerpc/xmon/ppc-opc.c {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, RS 5569 arch/powerpc/xmon/ppc-opc.c {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, RS 5570 arch/powerpc/xmon/ppc-opc.c {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, RS 5571 arch/powerpc/xmon/ppc-opc.c {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, RS 5572 arch/powerpc/xmon/ppc-opc.c {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, RS 5573 arch/powerpc/xmon/ppc-opc.c {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, RS 5574 arch/powerpc/xmon/ppc-opc.c {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, RS 5575 arch/powerpc/xmon/ppc-opc.c {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, RS 5576 arch/powerpc/xmon/ppc-opc.c {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, RS 5577 arch/powerpc/xmon/ppc-opc.c {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, RS 5578 arch/powerpc/xmon/ppc-opc.c {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, RS 5579 arch/powerpc/xmon/ppc-opc.c {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, RS 5580 arch/powerpc/xmon/ppc-opc.c {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, RS 5581 arch/powerpc/xmon/ppc-opc.c {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, RS 5582 arch/powerpc/xmon/ppc-opc.c {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, RS 5583 arch/powerpc/xmon/ppc-opc.c {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, RS 5584 arch/powerpc/xmon/ppc-opc.c {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, RS 5585 arch/powerpc/xmon/ppc-opc.c {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, RS 5586 arch/powerpc/xmon/ppc-opc.c {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, RS 5587 arch/powerpc/xmon/ppc-opc.c {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, RS 5588 arch/powerpc/xmon/ppc-opc.c {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, RS 5589 arch/powerpc/xmon/ppc-opc.c {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, RS 5590 arch/powerpc/xmon/ppc-opc.c {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, RS 5591 arch/powerpc/xmon/ppc-opc.c {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, RS 5592 arch/powerpc/xmon/ppc-opc.c {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, RS 5593 arch/powerpc/xmon/ppc-opc.c {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, RS 5594 arch/powerpc/xmon/ppc-opc.c {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, RS 5595 arch/powerpc/xmon/ppc-opc.c {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, RS 5596 arch/powerpc/xmon/ppc-opc.c {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, RS 5597 arch/powerpc/xmon/ppc-opc.c {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, RS 5598 arch/powerpc/xmon/ppc-opc.c {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, RS 5599 arch/powerpc/xmon/ppc-opc.c {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, RS 5600 arch/powerpc/xmon/ppc-opc.c {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, RS 5601 arch/powerpc/xmon/ppc-opc.c {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, RS 5602 arch/powerpc/xmon/ppc-opc.c {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, RS 5603 arch/powerpc/xmon/ppc-opc.c {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, RS 5604 arch/powerpc/xmon/ppc-opc.c {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, RS 5605 arch/powerpc/xmon/ppc-opc.c {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, RS 5606 arch/powerpc/xmon/ppc-opc.c {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, RS 5607 arch/powerpc/xmon/ppc-opc.c {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, RS 5608 arch/powerpc/xmon/ppc-opc.c {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, RS 5609 arch/powerpc/xmon/ppc-opc.c {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, RS 5610 arch/powerpc/xmon/ppc-opc.c {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, RS 5611 arch/powerpc/xmon/ppc-opc.c {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, RS 5612 arch/powerpc/xmon/ppc-opc.c {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, RS 5613 arch/powerpc/xmon/ppc-opc.c {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, RS 5614 arch/powerpc/xmon/ppc-opc.c {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, RS 5615 arch/powerpc/xmon/ppc-opc.c {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, RS 5616 arch/powerpc/xmon/ppc-opc.c {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, RS 5617 arch/powerpc/xmon/ppc-opc.c {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, RS 5618 arch/powerpc/xmon/ppc-opc.c {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, RS 5619 arch/powerpc/xmon/ppc-opc.c {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, RS 5620 arch/powerpc/xmon/ppc-opc.c {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, RS 5621 arch/powerpc/xmon/ppc-opc.c {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, RS 5622 arch/powerpc/xmon/ppc-opc.c {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, RS 5623 arch/powerpc/xmon/ppc-opc.c {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, RS 5624 arch/powerpc/xmon/ppc-opc.c {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, RS 5625 arch/powerpc/xmon/ppc-opc.c {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, RS 5626 arch/powerpc/xmon/ppc-opc.c {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, RS 5627 arch/powerpc/xmon/ppc-opc.c {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, RS 5628 arch/powerpc/xmon/ppc-opc.c {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, RS 5629 arch/powerpc/xmon/ppc-opc.c {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, RS 5630 arch/powerpc/xmon/ppc-opc.c {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, RS 5631 arch/powerpc/xmon/ppc-opc.c {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, RS 5632 arch/powerpc/xmon/ppc-opc.c {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, RS 5633 arch/powerpc/xmon/ppc-opc.c {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, RS 5634 arch/powerpc/xmon/ppc-opc.c {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, RS 5635 arch/powerpc/xmon/ppc-opc.c {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, RS 5636 arch/powerpc/xmon/ppc-opc.c {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, RS 5637 arch/powerpc/xmon/ppc-opc.c {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, RS 5638 arch/powerpc/xmon/ppc-opc.c {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, RS 5639 arch/powerpc/xmon/ppc-opc.c {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, RS 5640 arch/powerpc/xmon/ppc-opc.c {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, RS 5641 arch/powerpc/xmon/ppc-opc.c {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, RS 5642 arch/powerpc/xmon/ppc-opc.c {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, RS 5643 arch/powerpc/xmon/ppc-opc.c {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, RS 5644 arch/powerpc/xmon/ppc-opc.c {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, RS 5645 arch/powerpc/xmon/ppc-opc.c {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, RS 5646 arch/powerpc/xmon/ppc-opc.c {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, RS 5647 arch/powerpc/xmon/ppc-opc.c {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, RS 5648 arch/powerpc/xmon/ppc-opc.c {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, RS 5649 arch/powerpc/xmon/ppc-opc.c {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, RS 5650 arch/powerpc/xmon/ppc-opc.c {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, RS 5651 arch/powerpc/xmon/ppc-opc.c {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, RS 5652 arch/powerpc/xmon/ppc-opc.c {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, RS 5653 arch/powerpc/xmon/ppc-opc.c {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, RS 5654 arch/powerpc/xmon/ppc-opc.c {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, RS 5655 arch/powerpc/xmon/ppc-opc.c {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, RS 5656 arch/powerpc/xmon/ppc-opc.c {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, RS 5657 arch/powerpc/xmon/ppc-opc.c {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, RS 5658 arch/powerpc/xmon/ppc-opc.c {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, RS 5659 arch/powerpc/xmon/ppc-opc.c {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, RS 5660 arch/powerpc/xmon/ppc-opc.c {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, RS 5661 arch/powerpc/xmon/ppc-opc.c {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, RS 5662 arch/powerpc/xmon/ppc-opc.c {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, RS 5663 arch/powerpc/xmon/ppc-opc.c {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, RS 5664 arch/powerpc/xmon/ppc-opc.c {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, RS 5665 arch/powerpc/xmon/ppc-opc.c {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, RS 5666 arch/powerpc/xmon/ppc-opc.c {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, RS 5667 arch/powerpc/xmon/ppc-opc.c {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, RS 5668 arch/powerpc/xmon/ppc-opc.c {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, RS 5669 arch/powerpc/xmon/ppc-opc.c {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, RS 5670 arch/powerpc/xmon/ppc-opc.c {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, RS 5671 arch/powerpc/xmon/ppc-opc.c {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, RS 5672 arch/powerpc/xmon/ppc-opc.c {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, RS 5673 arch/powerpc/xmon/ppc-opc.c {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, RS 5674 arch/powerpc/xmon/ppc-opc.c {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, RS 5675 arch/powerpc/xmon/ppc-opc.c {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, RS 5676 arch/powerpc/xmon/ppc-opc.c {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, RS 5677 arch/powerpc/xmon/ppc-opc.c {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, RS 5678 arch/powerpc/xmon/ppc-opc.c {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, RS 5679 arch/powerpc/xmon/ppc-opc.c {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, RS 5680 arch/powerpc/xmon/ppc-opc.c {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, RS 5681 arch/powerpc/xmon/ppc-opc.c {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, RS 5682 arch/powerpc/xmon/ppc-opc.c {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, RS 5683 arch/powerpc/xmon/ppc-opc.c {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, RS 5684 arch/powerpc/xmon/ppc-opc.c {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, RS 5685 arch/powerpc/xmon/ppc-opc.c {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, RS 5686 arch/powerpc/xmon/ppc-opc.c {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, RS 5687 arch/powerpc/xmon/ppc-opc.c {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, RS 5688 arch/powerpc/xmon/ppc-opc.c {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, RS 5689 arch/powerpc/xmon/ppc-opc.c {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, RS 5690 arch/powerpc/xmon/ppc-opc.c {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, RS 5691 arch/powerpc/xmon/ppc-opc.c {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, RS 5692 arch/powerpc/xmon/ppc-opc.c {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, RS 5693 arch/powerpc/xmon/ppc-opc.c {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, RS 5694 arch/powerpc/xmon/ppc-opc.c {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, RS 5695 arch/powerpc/xmon/ppc-opc.c {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, RS 5696 arch/powerpc/xmon/ppc-opc.c {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, RS 5697 arch/powerpc/xmon/ppc-opc.c {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, RS 5698 arch/powerpc/xmon/ppc-opc.c {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, RS 5699 arch/powerpc/xmon/ppc-opc.c {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, RS 5700 arch/powerpc/xmon/ppc-opc.c {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, RS 5701 arch/powerpc/xmon/ppc-opc.c {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, RS 5702 arch/powerpc/xmon/ppc-opc.c {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, RS 5703 arch/powerpc/xmon/ppc-opc.c {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, RS 5704 arch/powerpc/xmon/ppc-opc.c {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, RS 5705 arch/powerpc/xmon/ppc-opc.c {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, RS 5706 arch/powerpc/xmon/ppc-opc.c {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, RS 5707 arch/powerpc/xmon/ppc-opc.c {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, RS 5708 arch/powerpc/xmon/ppc-opc.c {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, RS 5709 arch/powerpc/xmon/ppc-opc.c {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, RS 5710 arch/powerpc/xmon/ppc-opc.c {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, RS 5711 arch/powerpc/xmon/ppc-opc.c {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, RS 5712 arch/powerpc/xmon/ppc-opc.c {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, RS 5713 arch/powerpc/xmon/ppc-opc.c {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, RS 5714 arch/powerpc/xmon/ppc-opc.c {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, RS 5715 arch/powerpc/xmon/ppc-opc.c {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, RS 5716 arch/powerpc/xmon/ppc-opc.c {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, RS 5717 arch/powerpc/xmon/ppc-opc.c {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, RS 5721 arch/powerpc/xmon/ppc-opc.c {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, RS 5722 arch/powerpc/xmon/ppc-opc.c {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, RS 5748 arch/powerpc/xmon/ppc-opc.c {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, RS 5750 arch/powerpc/xmon/ppc-opc.c {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, RS 5788 arch/powerpc/xmon/ppc-opc.c {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 5789 arch/powerpc/xmon/ppc-opc.c {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 5790 arch/powerpc/xmon/ppc-opc.c {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 5791 arch/powerpc/xmon/ppc-opc.c {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 5793 arch/powerpc/xmon/ppc-opc.c {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5794 arch/powerpc/xmon/ppc-opc.c {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5796 arch/powerpc/xmon/ppc-opc.c {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, RS 5797 arch/powerpc/xmon/ppc-opc.c {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, RS 5799 arch/powerpc/xmon/ppc-opc.c {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 5800 arch/powerpc/xmon/ppc-opc.c {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 5802 arch/powerpc/xmon/ppc-opc.c {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5803 arch/powerpc/xmon/ppc-opc.c {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5824 arch/powerpc/xmon/ppc-opc.c {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, RS 5825 arch/powerpc/xmon/ppc-opc.c {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, RS 5876 arch/powerpc/xmon/ppc-opc.c {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, RS 5880 arch/powerpc/xmon/ppc-opc.c {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, RS 5881 arch/powerpc/xmon/ppc-opc.c {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, RS 5902 arch/powerpc/xmon/ppc-opc.c {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, RS 5904 arch/powerpc/xmon/ppc-opc.c {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, RS 5905 arch/powerpc/xmon/ppc-opc.c {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RS 5907 arch/powerpc/xmon/ppc-opc.c {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RS 5908 arch/powerpc/xmon/ppc-opc.c {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RS 5912 arch/powerpc/xmon/ppc-opc.c {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5913 arch/powerpc/xmon/ppc-opc.c {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5915 arch/powerpc/xmon/ppc-opc.c {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5916 arch/powerpc/xmon/ppc-opc.c {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5918 arch/powerpc/xmon/ppc-opc.c {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, RS 5919 arch/powerpc/xmon/ppc-opc.c {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, RS 5929 arch/powerpc/xmon/ppc-opc.c {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RS 5933 arch/powerpc/xmon/ppc-opc.c {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, RS 5934 arch/powerpc/xmon/ppc-opc.c {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, RS 5936 arch/powerpc/xmon/ppc-opc.c {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, RS 5937 arch/powerpc/xmon/ppc-opc.c {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, RS 5941 arch/powerpc/xmon/ppc-opc.c {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, RS 5959 arch/powerpc/xmon/ppc-opc.c {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, RS 5960 arch/powerpc/xmon/ppc-opc.c {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, RS 5962 arch/powerpc/xmon/ppc-opc.c {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RS 5966 arch/powerpc/xmon/ppc-opc.c {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5967 arch/powerpc/xmon/ppc-opc.c {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5969 arch/powerpc/xmon/ppc-opc.c {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 5970 arch/powerpc/xmon/ppc-opc.c {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 5975 arch/powerpc/xmon/ppc-opc.c {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, RS 5979 arch/powerpc/xmon/ppc-opc.c {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, RS 6012 arch/powerpc/xmon/ppc-opc.c {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, RS 6013 arch/powerpc/xmon/ppc-opc.c {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, RS 6048 arch/powerpc/xmon/ppc-opc.c {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 6049 arch/powerpc/xmon/ppc-opc.c {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 6050 arch/powerpc/xmon/ppc-opc.c {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RS 6051 arch/powerpc/xmon/ppc-opc.c {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RS 6053 arch/powerpc/xmon/ppc-opc.c {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 6054 arch/powerpc/xmon/ppc-opc.c {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RS 6069 arch/powerpc/xmon/ppc-opc.c {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, RS 6077 arch/powerpc/xmon/ppc-opc.c {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, RS 6078 arch/powerpc/xmon/ppc-opc.c {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, RS 6079 arch/powerpc/xmon/ppc-opc.c {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, RS 6080 arch/powerpc/xmon/ppc-opc.c {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, RS 6082 arch/powerpc/xmon/ppc-opc.c {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, RS 6083 arch/powerpc/xmon/ppc-opc.c {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, RS 6099 arch/powerpc/xmon/ppc-opc.c {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, RS 6132 arch/powerpc/xmon/ppc-opc.c {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, RS 6133 arch/powerpc/xmon/ppc-opc.c {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, RS 6156 arch/powerpc/xmon/ppc-opc.c {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, RS 6158 arch/powerpc/xmon/ppc-opc.c {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, RS 6163 arch/powerpc/xmon/ppc-opc.c {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 6164 arch/powerpc/xmon/ppc-opc.c {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 6166 arch/powerpc/xmon/ppc-opc.c {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, RS 6167 arch/powerpc/xmon/ppc-opc.c {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, RS 6169 arch/powerpc/xmon/ppc-opc.c {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, RS 6170 arch/powerpc/xmon/ppc-opc.c {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, RS 6171 arch/powerpc/xmon/ppc-opc.c {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, RS 6172 arch/powerpc/xmon/ppc-opc.c {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, RS 6198 arch/powerpc/xmon/ppc-opc.c {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, RS 6200 arch/powerpc/xmon/ppc-opc.c {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, RS 6201 arch/powerpc/xmon/ppc-opc.c {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, RS 6205 arch/powerpc/xmon/ppc-opc.c {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, RS 6206 arch/powerpc/xmon/ppc-opc.c {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, RS 6208 arch/powerpc/xmon/ppc-opc.c {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, RS 6209 arch/powerpc/xmon/ppc-opc.c {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, RS 6232 arch/powerpc/xmon/ppc-opc.c {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, RS 6238 arch/powerpc/xmon/ppc-opc.c {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, RS 6239 arch/powerpc/xmon/ppc-opc.c {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, RS 6262 arch/powerpc/xmon/ppc-opc.c {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, RS 6294 arch/powerpc/xmon/ppc-opc.c {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, RS 6295 arch/powerpc/xmon/ppc-opc.c {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RS 6297 arch/powerpc/xmon/ppc-opc.c {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, RS 6298 arch/powerpc/xmon/ppc-opc.c {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RS 6300 arch/powerpc/xmon/ppc-opc.c {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, RS 6302 arch/powerpc/xmon/ppc-opc.c {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, RS 6312 arch/powerpc/xmon/ppc-opc.c {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, RS 6314 arch/powerpc/xmon/ppc-opc.c {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, RS 6319 arch/powerpc/xmon/ppc-opc.c {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, RS 6320 arch/powerpc/xmon/ppc-opc.c {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RS 6673 arch/powerpc/xmon/ppc-opc.c {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, RS 6674 arch/powerpc/xmon/ppc-opc.c {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, RS 7026 arch/powerpc/xmon/ppc-opc.c {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7027 arch/powerpc/xmon/ppc-opc.c {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7029 arch/powerpc/xmon/ppc-opc.c {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7030 arch/powerpc/xmon/ppc-opc.c {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7031 arch/powerpc/xmon/ppc-opc.c {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7032 arch/powerpc/xmon/ppc-opc.c {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RS 7106 arch/powerpc/xmon/ppc-opc.c {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, RS 7155 arch/powerpc/xmon/ppc-opc.c {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 7156 arch/powerpc/xmon/ppc-opc.c {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 7160 arch/powerpc/xmon/ppc-opc.c {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RS 7161 arch/powerpc/xmon/ppc-opc.c {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RS 7166 arch/powerpc/xmon/ppc-opc.c {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 7167 arch/powerpc/xmon/ppc-opc.c {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 7174 arch/powerpc/xmon/ppc-opc.c {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, RS 7176 arch/powerpc/xmon/ppc-opc.c {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 7177 arch/powerpc/xmon/ppc-opc.c {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RS 784 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 794 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 804 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 814 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, C(11), R(12), R(13), RS 824 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 834 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 844 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), RS 854 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, C(11), R(12), R(13), RS 864 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), RS 874 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), RS 884 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), RS 894 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, C(11), R(12), R(13), RS 951 drivers/edac/pnd2_edac.c if (type == RS && (cr_drp0->rken0 + cr_drp0->rken1) == 1) { RS 969 drivers/edac/pnd2_edac.c case RS: RS 38 drivers/macintosh/via-cuda.c #define A RS /* A-side data */ RS 39 drivers/macintosh/via-cuda.c #define DIRB (2*RS) /* B-side direction (1=output) */ RS 40 drivers/macintosh/via-cuda.c #define DIRA (3*RS) /* A-side direction (1=output) */ RS 41 drivers/macintosh/via-cuda.c #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ RS 42 drivers/macintosh/via-cuda.c #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ RS 43 drivers/macintosh/via-cuda.c #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ RS 44 drivers/macintosh/via-cuda.c #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ RS 45 drivers/macintosh/via-cuda.c #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ RS 46 drivers/macintosh/via-cuda.c #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */ RS 47 drivers/macintosh/via-cuda.c #define SR (10*RS) /* Shift register */ RS 48 drivers/macintosh/via-cuda.c #define ACR (11*RS) /* Auxiliary control register */ RS 49 drivers/macintosh/via-cuda.c #define PCR (12*RS) /* Peripheral control register */ RS 50 drivers/macintosh/via-cuda.c #define IFR (13*RS) /* Interrupt flag register */ RS 51 drivers/macintosh/via-cuda.c #define IER (14*RS) /* Interrupt enable register */ RS 52 drivers/macintosh/via-cuda.c #define ANH (15*RS) /* A-side data, no handshake */ RS 44 drivers/macintosh/via-macii.c #define A RS /* A-side data */ RS 45 drivers/macintosh/via-macii.c #define DIRB (2*RS) /* B-side direction (1=output) */ RS 46 drivers/macintosh/via-macii.c #define DIRA (3*RS) /* A-side direction (1=output) */ RS 47 drivers/macintosh/via-macii.c #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ RS 48 drivers/macintosh/via-macii.c #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ RS 49 drivers/macintosh/via-macii.c #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ RS 50 drivers/macintosh/via-macii.c #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ RS 51 drivers/macintosh/via-macii.c #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ RS 52 drivers/macintosh/via-macii.c #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */ RS 53 drivers/macintosh/via-macii.c #define SR (10*RS) /* Shift register */ RS 54 drivers/macintosh/via-macii.c #define ACR (11*RS) /* Auxiliary control register */ RS 55 drivers/macintosh/via-macii.c #define PCR (12*RS) /* Peripheral control register */ RS 56 drivers/macintosh/via-macii.c #define IFR (13*RS) /* Interrupt flag register */ RS 57 drivers/macintosh/via-macii.c #define IER (14*RS) /* Interrupt enable register */ RS 58 drivers/macintosh/via-macii.c #define ANH (15*RS) /* A-side data, no handshake */ RS 89 drivers/macintosh/via-pmu.c #define A RS /* A-side data */ RS 90 drivers/macintosh/via-pmu.c #define DIRB (2*RS) /* B-side direction (1=output) */ RS 91 drivers/macintosh/via-pmu.c #define DIRA (3*RS) /* A-side direction (1=output) */ RS 92 drivers/macintosh/via-pmu.c #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ RS 93 drivers/macintosh/via-pmu.c #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ RS 94 drivers/macintosh/via-pmu.c #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ RS 95 drivers/macintosh/via-pmu.c #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ RS 96 drivers/macintosh/via-pmu.c #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */ RS 97 drivers/macintosh/via-pmu.c #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */ RS 98 drivers/macintosh/via-pmu.c #define SR (10*RS) /* Shift register */ RS 99 drivers/macintosh/via-pmu.c #define ACR (11*RS) /* Auxiliary control register */ RS 100 drivers/macintosh/via-pmu.c #define PCR (12*RS) /* Peripheral control register */ RS 101 drivers/macintosh/via-pmu.c #define IFR (13*RS) /* Interrupt flag register */ RS 102 drivers/macintosh/via-pmu.c #define IER (14*RS) /* Interrupt enable register */ RS 103 drivers/macintosh/via-pmu.c #define ANH (15*RS) /* A-side data, no handshake */ RS 205 drivers/staging/fbtft/fb_agm1264k-fl.c gpiod_set_value(par->RS, 0); /* RS->0 (command mode) */ RS 367 drivers/staging/fbtft/fb_agm1264k-fl.c gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */ RS 390 drivers/staging/fbtft/fb_agm1264k-fl.c gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */ RS 23 tools/testing/selftests/powerpc/primitives/asm/asm-compat.h #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS) RS 422 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define MTOCRF(FXM, RS) \ RS 424 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h mtcrf (FXM), RS; \ RS 426 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h mtocrf (FXM), RS; \