RREG32_SOC15 66 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \ RREG32_SOC15 109 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); \ RREG32_SOC15 37 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 53 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 96 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 40 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 57 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 96 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); RREG32_SOC15 42 drivers/gpu/drm/amd/amdgpu/df_v1_7.c tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); RREG32_SOC15 54 drivers/gpu/drm/amd/amdgpu/df_v1_7.c tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); RREG32_SOC15 79 drivers/gpu/drm/amd/amdgpu/df_v1_7.c tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); RREG32_SOC15 84 drivers/gpu/drm/amd/amdgpu/df_v1_7.c tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); RREG32_SOC15 100 drivers/gpu/drm/amd/amdgpu/df_v1_7.c tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); RREG32_SOC15 229 drivers/gpu/drm/amd/amdgpu/df_v3_6.c tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); RREG32_SOC15 241 drivers/gpu/drm/amd/amdgpu/df_v3_6.c tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); RREG32_SOC15 269 drivers/gpu/drm/amd/amdgpu/df_v3_6.c tmp = RREG32_SOC15(DF, 0, RREG32_SOC15 276 drivers/gpu/drm/amd/amdgpu/df_v3_6.c tmp = RREG32_SOC15(DF, 0, RREG32_SOC15 295 drivers/gpu/drm/amd/amdgpu/df_v3_6.c tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); RREG32_SOC15 1115 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); RREG32_SOC15 1128 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); RREG32_SOC15 1209 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); RREG32_SOC15 1526 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); RREG32_SOC15 1527 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); RREG32_SOC15 1702 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); RREG32_SOC15 1708 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); RREG32_SOC15 1724 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | RREG32_SOC15 1725 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); RREG32_SOC15 1774 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); RREG32_SOC15 1838 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); RREG32_SOC15 1857 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); RREG32_SOC15 2227 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); RREG32_SOC15 2234 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); RREG32_SOC15 2251 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); RREG32_SOC15 2257 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); RREG32_SOC15 2288 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); RREG32_SOC15 2294 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); RREG32_SOC15 2325 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); RREG32_SOC15 2331 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); RREG32_SOC15 2362 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); RREG32_SOC15 2368 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); RREG32_SOC15 2398 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); RREG32_SOC15 2399 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); RREG32_SOC15 2437 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); RREG32_SOC15 2449 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) RREG32_SOC15 2495 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); RREG32_SOC15 2501 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); RREG32_SOC15 2516 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); RREG32_SOC15 2565 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); RREG32_SOC15 2571 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); RREG32_SOC15 2586 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); RREG32_SOC15 2634 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); RREG32_SOC15 2640 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); RREG32_SOC15 2655 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); RREG32_SOC15 2781 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); RREG32_SOC15 2792 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); RREG32_SOC15 2955 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); RREG32_SOC15 2961 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); RREG32_SOC15 2976 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); RREG32_SOC15 3010 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); RREG32_SOC15 3035 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); RREG32_SOC15 3042 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); RREG32_SOC15 3048 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); RREG32_SOC15 3053 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); RREG32_SOC15 3075 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); RREG32_SOC15 3084 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); RREG32_SOC15 3097 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); RREG32_SOC15 3280 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); RREG32_SOC15 3287 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32_SOC15 3317 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); RREG32_SOC15 3327 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); RREG32_SOC15 3355 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32_SOC15 3371 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); RREG32_SOC15 3376 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); RREG32_SOC15 3381 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); RREG32_SOC15 3415 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { RREG32_SOC15 3418 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) RREG32_SOC15 3692 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); RREG32_SOC15 3698 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { RREG32_SOC15 3887 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), RREG32_SOC15 3902 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & RREG32_SOC15 3919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); RREG32_SOC15 3941 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); RREG32_SOC15 3958 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 3962 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 3968 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 3984 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | RREG32_SOC15 3985 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32_SOC15 4057 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); RREG32_SOC15 4072 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) RREG32_SOC15 4094 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4109 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4124 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4133 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4140 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4156 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4163 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4173 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); RREG32_SOC15 4180 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4196 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4208 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4218 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); RREG32_SOC15 4224 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4325 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4330 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4339 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4344 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4349 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4372 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); RREG32_SOC15 4373 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; RREG32_SOC15 5131 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); RREG32_SOC15 5141 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); RREG32_SOC15 5404 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); RREG32_SOC15 5405 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); RREG32_SOC15 1560 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); RREG32_SOC15 1609 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); RREG32_SOC15 1783 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); RREG32_SOC15 1798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); RREG32_SOC15 1888 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); RREG32_SOC15 1913 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); RREG32_SOC15 1923 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); RREG32_SOC15 2027 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); RREG32_SOC15 2028 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); RREG32_SOC15 2404 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); RREG32_SOC15 2405 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); RREG32_SOC15 2510 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); RREG32_SOC15 2556 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) RREG32_SOC15 2578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) RREG32_SOC15 2587 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); RREG32_SOC15 2979 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); RREG32_SOC15 3067 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); RREG32_SOC15 3243 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); RREG32_SOC15 3334 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); RREG32_SOC15 3441 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); RREG32_SOC15 3448 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32_SOC15 3478 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); RREG32_SOC15 3488 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); RREG32_SOC15 3516 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32_SOC15 3532 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); RREG32_SOC15 3537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); RREG32_SOC15 3542 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); RREG32_SOC15 3575 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { RREG32_SOC15 3578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) RREG32_SOC15 3663 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { RREG32_SOC15 3668 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) RREG32_SOC15 3999 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), RREG32_SOC15 4026 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); RREG32_SOC15 4045 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); RREG32_SOC15 4063 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 4067 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 4073 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); RREG32_SOC15 4089 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | RREG32_SOC15 4090 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32_SOC15 4545 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); RREG32_SOC15 4563 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) RREG32_SOC15 4626 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4645 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4652 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4660 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4674 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4681 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4704 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4712 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4723 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); RREG32_SOC15 4730 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4750 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4762 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4777 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); RREG32_SOC15 4783 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4912 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); RREG32_SOC15 4917 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); RREG32_SOC15 4926 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); RREG32_SOC15 4931 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); RREG32_SOC15 4937 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); RREG32_SOC15 4961 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); RREG32_SOC15 4962 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; RREG32_SOC15 6439 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); RREG32_SOC15 6440 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); RREG32_SOC15 35 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; RREG32_SOC15 119 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 140 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); RREG32_SOC15 151 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); RREG32_SOC15 178 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); RREG32_SOC15 301 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 324 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); RREG32_SOC15 33 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); RREG32_SOC15 48 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), RREG32_SOC15 36 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); RREG32_SOC15 46 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; RREG32_SOC15 115 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 135 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); RREG32_SOC15 148 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); RREG32_SOC15 175 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); RREG32_SOC15 289 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 310 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); RREG32_SOC15 666 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); RREG32_SOC15 675 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); RREG32_SOC15 676 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); RREG32_SOC15 846 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); RREG32_SOC15 850 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); RREG32_SOC15 1148 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); RREG32_SOC15 1157 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); RREG32_SOC15 1168 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); RREG32_SOC15 1443 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); RREG32_SOC15 192 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); RREG32_SOC15 201 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); RREG32_SOC15 210 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); RREG32_SOC15 270 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); RREG32_SOC15 276 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); RREG32_SOC15 43 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); RREG32_SOC15 44 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); RREG32_SOC15 134 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); RREG32_SOC15 145 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 169 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); RREG32_SOC15 180 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); RREG32_SOC15 206 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); RREG32_SOC15 346 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 356 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); RREG32_SOC15 376 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); RREG32_SOC15 441 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); RREG32_SOC15 444 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); RREG32_SOC15 445 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); RREG32_SOC15 447 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); RREG32_SOC15 504 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); RREG32_SOC15 546 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); RREG32_SOC15 548 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); RREG32_SOC15 574 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20); RREG32_SOC15 575 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20); RREG32_SOC15 576 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20); RREG32_SOC15 577 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20); RREG32_SOC15 90 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); RREG32_SOC15 101 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 121 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); RREG32_SOC15 134 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); RREG32_SOC15 161 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); RREG32_SOC15 279 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); RREG32_SOC15 286 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); RREG32_SOC15 301 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); RREG32_SOC15 364 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); RREG32_SOC15 366 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); RREG32_SOC15 401 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); RREG32_SOC15 441 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); RREG32_SOC15 443 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); RREG32_SOC15 41 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); RREG32_SOC15 42 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP); RREG32_SOC15 639 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); RREG32_SOC15 641 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); RREG32_SOC15 47 drivers/gpu/drm/amd/amdgpu/navi10_ih.c u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 64 drivers/gpu/drm/amd/amdgpu/navi10_ih.c u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 126 drivers/gpu/drm/amd/amdgpu/navi10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 133 drivers/gpu/drm/amd/amdgpu/navi10_ih.c ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); RREG32_SOC15 152 drivers/gpu/drm/amd/amdgpu/navi10_ih.c ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); RREG32_SOC15 168 drivers/gpu/drm/amd/amdgpu/navi10_ih.c tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); RREG32_SOC15 173 drivers/gpu/drm/amd/amdgpu/navi10_ih.c tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); RREG32_SOC15 405 drivers/gpu/drm/amd/amdgpu/navi10_ih.c def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); RREG32_SOC15 444 drivers/gpu/drm/amd/amdgpu/navi10_ih.c if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) RREG32_SOC15 37 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); RREG32_SOC15 67 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); RREG32_SOC15 148 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); RREG32_SOC15 172 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); RREG32_SOC15 288 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER); RREG32_SOC15 35 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); RREG32_SOC15 67 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); RREG32_SOC15 117 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); RREG32_SOC15 135 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); RREG32_SOC15 248 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); RREG32_SOC15 46 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); RREG32_SOC15 74 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); RREG32_SOC15 129 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); RREG32_SOC15 145 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); RREG32_SOC15 238 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); RREG32_SOC15 63 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); RREG32_SOC15 91 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); RREG32_SOC15 179 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); RREG32_SOC15 239 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); RREG32_SOC15 294 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); RREG32_SOC15 527 drivers/gpu/drm/amd/amdgpu/nv.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 760 drivers/gpu/drm/amd/amdgpu/nv.c hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); RREG32_SOC15 761 drivers/gpu/drm/amd/amdgpu/nv.c hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); RREG32_SOC15 830 drivers/gpu/drm/amd/amdgpu/nv.c hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); RREG32_SOC15 898 drivers/gpu/drm/amd/amdgpu/nv.c tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); RREG32_SOC15 908 drivers/gpu/drm/amd/amdgpu/nv.c tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); RREG32_SOC15 207 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); RREG32_SOC15 218 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 220 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); RREG32_SOC15 260 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 262 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); RREG32_SOC15 304 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 329 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15 523 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); RREG32_SOC15 525 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); RREG32_SOC15 97 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 99 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); RREG32_SOC15 141 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 166 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15 353 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); RREG32_SOC15 355 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); RREG32_SOC15 140 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 200 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 202 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); RREG32_SOC15 228 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15 231 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); RREG32_SOC15 429 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); RREG32_SOC15 431 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); RREG32_SOC15 55 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); RREG32_SOC15 74 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); RREG32_SOC15 142 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); RREG32_SOC15 150 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); RREG32_SOC15 153 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); RREG32_SOC15 184 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); RREG32_SOC15 203 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); RREG32_SOC15 254 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); RREG32_SOC15 280 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); RREG32_SOC15 380 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); RREG32_SOC15 424 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); RREG32_SOC15 425 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); RREG32_SOC15 442 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY); RREG32_SOC15 482 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); RREG32_SOC15 483 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); RREG32_SOC15 233 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); RREG32_SOC15 255 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); RREG32_SOC15 944 drivers/gpu/drm/amd/amdgpu/soc15.c sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); RREG32_SOC15 57 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c rsmu_umc_index = RREG32_SOC15(RSMU, 0, RREG32_SOC15 75 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); RREG32_SOC15 90 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); RREG32_SOC15 92 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); RREG32_SOC15 106 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); RREG32_SOC15 124 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); RREG32_SOC15 126 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); RREG32_SOC15 379 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); RREG32_SOC15 724 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); RREG32_SOC15 746 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); RREG32_SOC15 750 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); RREG32_SOC15 1027 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c status = RREG32_SOC15(UVD, k, mmUVD_STATUS); RREG32_SOC15 1086 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1241 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); RREG32_SOC15 1462 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & RREG32_SOC15 1585 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); RREG32_SOC15 1586 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); RREG32_SOC15 1587 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 1641 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); RREG32_SOC15 1642 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); RREG32_SOC15 237 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(VCN, 0, mmUVD_STATUS)) RREG32_SOC15 446 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); RREG32_SOC15 457 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); RREG32_SOC15 462 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 472 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); RREG32_SOC15 495 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 519 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); RREG32_SOC15 546 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 573 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); RREG32_SOC15 582 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); RREG32_SOC15 587 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 596 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 619 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 725 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); RREG32_SOC15 740 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); RREG32_SOC15 794 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; RREG32_SOC15 805 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); RREG32_SOC15 818 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); RREG32_SOC15 844 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); RREG32_SOC15 857 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); RREG32_SOC15 866 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); RREG32_SOC15 900 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; RREG32_SOC15 930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 962 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); RREG32_SOC15 1103 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1112 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 1191 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); RREG32_SOC15 1194 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); RREG32_SOC15 1197 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 1200 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; RREG32_SOC15 1240 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & RREG32_SOC15 1276 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); RREG32_SOC15 1295 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & RREG32_SOC15 1308 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); RREG32_SOC15 1336 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); RREG32_SOC15 1356 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); RREG32_SOC15 1399 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1413 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); RREG32_SOC15 1602 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); RREG32_SOC15 1604 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); RREG32_SOC15 1619 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); RREG32_SOC15 1621 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); RREG32_SOC15 1732 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); RREG32_SOC15 1746 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 298 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c RREG32_SOC15(VCN, 0, mmUVD_STATUS))) RREG32_SOC15 514 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 523 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); RREG32_SOC15 546 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 570 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); RREG32_SOC15 597 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 690 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); RREG32_SOC15 696 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); RREG32_SOC15 723 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 746 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); RREG32_SOC15 753 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); RREG32_SOC15 795 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 804 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); RREG32_SOC15 827 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 879 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); RREG32_SOC15 895 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); RREG32_SOC15 936 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); RREG32_SOC15 1047 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1074 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; RREG32_SOC15 1089 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); RREG32_SOC15 1097 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); RREG32_SOC15 1132 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); RREG32_SOC15 1149 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); RREG32_SOC15 1203 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1237 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); RREG32_SOC15 1240 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); RREG32_SOC15 1243 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 1246 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; RREG32_SOC15 1289 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); RREG32_SOC15 1342 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & RREG32_SOC15 1376 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); RREG32_SOC15 1397 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); RREG32_SOC15 1440 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); RREG32_SOC15 1457 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); RREG32_SOC15 1661 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); RREG32_SOC15 1663 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); RREG32_SOC15 1681 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); RREG32_SOC15 1686 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); RREG32_SOC15 1804 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); RREG32_SOC15 1821 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 81 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING); RREG32_SOC15 310 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) RREG32_SOC15 439 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); RREG32_SOC15 448 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); RREG32_SOC15 474 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); RREG32_SOC15 498 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); RREG32_SOC15 525 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 556 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); RREG32_SOC15 565 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); RREG32_SOC15 587 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); RREG32_SOC15 624 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); RREG32_SOC15 630 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE); RREG32_SOC15 637 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); RREG32_SOC15 669 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 695 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE); RREG32_SOC15 725 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; RREG32_SOC15 744 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL); RREG32_SOC15 753 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL); RREG32_SOC15 805 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c status = RREG32_SOC15(UVD, i, mmUVD_STATUS); RREG32_SOC15 864 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR); RREG32_SOC15 912 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); RREG32_SOC15 961 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); RREG32_SOC15 978 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); RREG32_SOC15 1042 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); RREG32_SOC15 1044 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); RREG32_SOC15 1062 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); RREG32_SOC15 1067 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); RREG32_SOC15 1140 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR); RREG32_SOC15 1157 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR); RREG32_SOC15 1258 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); RREG32_SOC15 49 drivers/gpu/drm/amd/amdgpu/vega10_ih.c u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 64 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); RREG32_SOC15 80 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); RREG32_SOC15 105 drivers/gpu/drm/amd/amdgpu/vega10_ih.c u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 125 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); RREG32_SOC15 145 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); RREG32_SOC15 236 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); RREG32_SOC15 237 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); RREG32_SOC15 280 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); RREG32_SOC15 310 drivers/gpu/drm/amd/amdgpu/vega10_ih.c ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); RREG32_SOC15 331 drivers/gpu/drm/amd/amdgpu/vega10_ih.c tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); RREG32_SOC15 336 drivers/gpu/drm/amd/amdgpu/vega10_ih.c tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); RREG32_SOC15 314 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); RREG32_SOC15 1104 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); RREG32_SOC15 44 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); RREG32_SOC15 58 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); RREG32_SOC15 931 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & RREG32_SOC15 3826 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & RREG32_SOC15 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), RREG32_SOC15 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 167 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), RREG32_SOC15 279 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), RREG32_SOC15 327 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), RREG32_SOC15 344 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); RREG32_SOC15 382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); RREG32_SOC15 408 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), RREG32_SOC15 414 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 151 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); RREG32_SOC15 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); RREG32_SOC15 50 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); RREG32_SOC15 64 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); RREG32_SOC15 89 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); RREG32_SOC15 2223 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & RREG32_SOC15 95 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 98 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 150 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), RREG32_SOC15 161 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), RREG32_SOC15 204 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), RREG32_SOC15 221 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); RREG32_SOC15 258 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); RREG32_SOC15 68 drivers/gpu/drm/amd/powerplay/smu_v11_0.c *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); RREG32_SOC15 78 drivers/gpu/drm/amd/powerplay/smu_v11_0.c cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); RREG32_SOC15 88 drivers/gpu/drm/amd/powerplay/smu_v11_0.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; RREG32_SOC15 1149 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); RREG32_SOC15 1231 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & RREG32_SOC15 1413 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 1416 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), RREG32_SOC15 1435 drivers/gpu/drm/amd/powerplay/smu_v11_0.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), RREG32_SOC15 1445 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), RREG32_SOC15 1497 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), RREG32_SOC15 1661 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); RREG32_SOC15 57 drivers/gpu/drm/amd/powerplay/smu_v12_0.c *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); RREG32_SOC15 67 drivers/gpu/drm/amd/powerplay/smu_v12_0.c cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); RREG32_SOC15 77 drivers/gpu/drm/amd/powerplay/smu_v12_0.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO; RREG32_SOC15 233 drivers/gpu/drm/amd/powerplay/smu_v12_0.c reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); RREG32_SOC15 59 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); RREG32_SOC15 76 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); RREG32_SOC15 72 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); RREG32_SOC15 147 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); RREG32_SOC15 78 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); RREG32_SOC15 153 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); RREG32_SOC15 2994 drivers/gpu/drm/amd/powerplay/vega20_ppt.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);