RREG32_SMC 68 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c return RREG32_SMC(index); RREG32_SMC 401 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c value = RREG32_SMC(*pos); RREG32_SMC 846 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) RREG32_SMC 849 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) RREG32_SMC 906 drivers/gpu/drm/amd/amdgpu/cik.c rom_cntl = RREG32_SMC(ixROM_CNTL); RREG32_SMC 1318 drivers/gpu/drm/amd/amdgpu/cik.c tmp = RREG32_SMC(cntl_reg); RREG32_SMC 1325 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) RREG32_SMC 1360 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) RREG32_SMC 1367 drivers/gpu/drm/amd/amdgpu/cik.c tmp = RREG32_SMC(ixCG_ECLK_CNTL); RREG32_SMC 1374 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) RREG32_SMC 1651 drivers/gpu/drm/amd/amdgpu/cik.c orig = data = RREG32_SMC(ixTHM_CLK_CNTL); RREG32_SMC 1659 drivers/gpu/drm/amd/amdgpu/cik.c orig = data = RREG32_SMC(ixMISC_CLK_CTRL); RREG32_SMC 1667 drivers/gpu/drm/amd/amdgpu/cik.c orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); RREG32_SMC 1672 drivers/gpu/drm/amd/amdgpu/cik.c orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); RREG32_SMC 1677 drivers/gpu/drm/amd/amdgpu/cik.c orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); RREG32_SMC 1805 drivers/gpu/drm/amd/amdgpu/cik.c clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 1806 drivers/gpu/drm/amd/amdgpu/cik.c pc = RREG32_SMC(ixSMC_PC_C); RREG32_SMC 426 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data = RREG32_SMC(config_regs->offset); RREG32_SMC 727 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); RREG32_SMC 742 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); RREG32_SMC 753 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); RREG32_SMC 2507 drivers/gpu/drm/amd/amdgpu/kv_dpm.c nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); RREG32_SMC 2536 drivers/gpu/drm/amd/amdgpu/kv_dpm.c tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); RREG32_SMC 2870 drivers/gpu/drm/amd/amdgpu/kv_dpm.c (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 2880 drivers/gpu/drm/amd/amdgpu/kv_dpm.c tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & RREG32_SMC 2955 drivers/gpu/drm/amd/amdgpu/kv_dpm.c temp = RREG32_SMC(0xC0300E0C); RREG32_SMC 3149 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); RREG32_SMC 3154 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); RREG32_SMC 3166 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); RREG32_SMC 3171 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); RREG32_SMC 3287 drivers/gpu/drm/amd/amdgpu/kv_dpm.c (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 63 drivers/gpu/drm/amd/amdgpu/kv_smc.c *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); RREG32_SMC 2851 drivers/gpu/drm/amd/amdgpu/si_dpm.c data = RREG32_SMC(offset); RREG32_SMC 7515 drivers/gpu/drm/amd/amdgpu/si_dpm.c cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 7520 drivers/gpu/drm/amd/amdgpu/si_dpm.c cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 7532 drivers/gpu/drm/amd/amdgpu/si_dpm.c cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 7537 drivers/gpu/drm/amd/amdgpu/si_dpm.c cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 113 drivers/gpu/drm/amd/amdgpu/si_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 129 drivers/gpu/drm/amd/amdgpu/si_smc.c tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | RREG32_SMC 143 drivers/gpu/drm/amd/amdgpu/si_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 155 drivers/gpu/drm/amd/amdgpu/si_smc.c u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 156 drivers/gpu/drm/amd/amdgpu/si_smc.c u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 194 drivers/gpu/drm/amd/amdgpu/si_smc.c tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 700 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & RREG32_SMC 711 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c if (RREG32_SMC(ixCURRENT_PG_STATUS) & RREG32_SMC 816 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c if (RREG32_SMC(ixCURRENT_PG_STATUS) & RREG32_SMC 368 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) RREG32_SMC 1476 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); RREG32_SMC 1478 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32_SMC(ixCURRENT_PG_STATUS); RREG32_SMC 1680 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); RREG32_SMC 373 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & RREG32_SMC 377 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & RREG32_SMC 814 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); RREG32_SMC 816 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32_SMC(ixCURRENT_PG_STATUS); RREG32_SMC 876 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); RREG32_SMC 335 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); RREG32_SMC 339 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); RREG32_SMC 390 drivers/gpu/drm/amd/amdgpu/vi.c rom_cntl = RREG32_SMC(ixROM_CNTL); RREG32_SMC 738 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(cntl_reg); RREG32_SMC 749 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(status_reg); RREG32_SMC 825 drivers/gpu/drm/amd/amdgpu/vi.c if (RREG32_SMC(reg_status) & status_mask) RREG32_SMC 833 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(reg_ctrl); RREG32_SMC 839 drivers/gpu/drm/amd/amdgpu/vi.c if (RREG32_SMC(reg_status) & status_mask) RREG32_SMC 902 drivers/gpu/drm/amd/amdgpu/vi.c return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) RREG32_SMC 1017 drivers/gpu/drm/amd/amdgpu/vi.c clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 1018 drivers/gpu/drm/amd/amdgpu/vi.c pc = RREG32_SMC(ixSMC_PC_C); RREG32_SMC 1431 drivers/gpu/drm/amd/amdgpu/vi.c temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); RREG32_SMC 1640 drivers/gpu/drm/amd/amdgpu/vi.c data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); RREG32_SMC 584 drivers/gpu/drm/radeon/ci_dpm.c data = RREG32_SMC(config_regs->offset); RREG32_SMC 886 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 894 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_THERMAL_CTRL); RREG32_SMC 909 drivers/gpu/drm/radeon/ci_dpm.c u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); RREG32_SMC 941 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; RREG32_SMC 943 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; RREG32_SMC 948 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32_SMC 952 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32_SMC 973 drivers/gpu/drm/radeon/ci_dpm.c duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32_SMC 1017 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; RREG32_SMC 1084 drivers/gpu/drm/radeon/ci_dpm.c duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32_SMC 1085 drivers/gpu/drm/radeon/ci_dpm.c duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; RREG32_SMC 1117 drivers/gpu/drm/radeon/ci_dpm.c duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32_SMC 1126 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; RREG32_SMC 1157 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; RREG32_SMC 1174 drivers/gpu/drm/radeon/ci_dpm.c tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; RREG32_SMC 1203 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; RREG32_SMC 1219 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32_SMC 1223 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32_SMC 1243 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; RREG32_SMC 1248 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; RREG32_SMC 1410 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_THERMAL_CTRL); RREG32_SMC 1416 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1423 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1533 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1537 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 1594 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1598 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 1621 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 1805 drivers/gpu/drm/radeon/ci_dpm.c if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED) RREG32_SMC 1875 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL); RREG32_SMC 1877 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL_2); RREG32_SMC 1879 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL_3); RREG32_SMC 1881 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL_4); RREG32_SMC 1883 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); RREG32_SMC 1885 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2); RREG32_SMC 1907 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1918 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 1987 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); RREG32_SMC 2026 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 2031 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM); RREG32_SMC 2035 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 2048 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); RREG32_SMC 2061 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 2079 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 2099 drivers/gpu/drm/radeon/ci_dpm.c if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) RREG32_SMC 2487 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; RREG32_SMC 4090 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(DPM_TABLE_475); RREG32_SMC 4128 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(DPM_TABLE_475); RREG32_SMC 4158 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(DPM_TABLE_475); RREG32_SMC 4225 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & RREG32_SMC 4244 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 4263 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 4280 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 4295 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & RREG32_SMC 4310 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) & RREG32_SMC 4791 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 5849 drivers/gpu/drm/radeon/ci_dpm.c u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL); RREG32_SMC 116 drivers/gpu/drm/radeon/ci_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 124 drivers/gpu/drm/radeon/ci_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 139 drivers/gpu/drm/radeon/ci_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 148 drivers/gpu/drm/radeon/ci_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 157 drivers/gpu/drm/radeon/ci_smc.c u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 158 drivers/gpu/drm/radeon/ci_smc.c u32 pc_c = RREG32_SMC(SMC_PC_C); RREG32_SMC 176 drivers/gpu/drm/radeon/ci_smc.c tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 216 drivers/gpu/drm/radeon/cik.c temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> RREG32_SMC 235 drivers/gpu/drm/radeon/cik.c temp = RREG32_SMC(0xC0300E0C); RREG32_SMC 1723 drivers/gpu/drm/radeon/cik.c if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) RREG32_SMC 1726 drivers/gpu/drm/radeon/cik.c if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) RREG32_SMC 9440 drivers/gpu/drm/radeon/cik.c tmp = RREG32_SMC(cntl_reg); RREG32_SMC 9446 drivers/gpu/drm/radeon/cik.c if (RREG32_SMC(status_reg) & DCLK_STATUS) RREG32_SMC 9480 drivers/gpu/drm/radeon/cik.c if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) RREG32_SMC 9487 drivers/gpu/drm/radeon/cik.c tmp = RREG32_SMC(CG_ECLK_CNTL); RREG32_SMC 9493 drivers/gpu/drm/radeon/cik.c if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) RREG32_SMC 9761 drivers/gpu/drm/radeon/cik.c orig = data = RREG32_SMC(THM_CLK_CNTL); RREG32_SMC 9767 drivers/gpu/drm/radeon/cik.c orig = data = RREG32_SMC(MISC_CLK_CTRL); RREG32_SMC 9773 drivers/gpu/drm/radeon/cik.c orig = data = RREG32_SMC(CG_CLKPIN_CNTL); RREG32_SMC 9778 drivers/gpu/drm/radeon/cik.c orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2); RREG32_SMC 9783 drivers/gpu/drm/radeon/cik.c orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL); RREG32_SMC 300 drivers/gpu/drm/radeon/kv_dpm.c data = RREG32_SMC(config_regs->offset); RREG32_SMC 647 drivers/gpu/drm/radeon/kv_dpm.c u32 tmp = RREG32_SMC(GENERAL_PWRMGT); RREG32_SMC 662 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 672 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); RREG32_SMC 1178 drivers/gpu/drm/radeon/kv_dpm.c thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); RREG32_SMC 2442 drivers/gpu/drm/radeon/kv_dpm.c nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); RREG32_SMC 2469 drivers/gpu/drm/radeon/kv_dpm.c tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); RREG32_SMC 2807 drivers/gpu/drm/radeon/kv_dpm.c (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> RREG32_SMC 2816 drivers/gpu/drm/radeon/kv_dpm.c tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> RREG32_SMC 2830 drivers/gpu/drm/radeon/kv_dpm.c (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> RREG32_SMC 60 drivers/gpu/drm/radeon/kv_smc.c *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); RREG32_SMC 882 drivers/gpu/drm/radeon/ni.c u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; RREG32_SMC 2560 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_SMC(reg); \ RREG32_SMC 7468 drivers/gpu/drm/radeon/si.c if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) RREG32_SMC 2752 drivers/gpu/drm/radeon/si_dpm.c data = RREG32_SMC(offset); RREG32_SMC 115 drivers/gpu/drm/radeon/si_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 131 drivers/gpu/drm/radeon/si_smc.c tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 145 drivers/gpu/drm/radeon/si_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 154 drivers/gpu/drm/radeon/si_smc.c u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 163 drivers/gpu/drm/radeon/si_smc.c u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); RREG32_SMC 164 drivers/gpu/drm/radeon/si_smc.c u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 202 drivers/gpu/drm/radeon/si_smc.c tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); RREG32_SMC 379 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(GFX_POWER_GATING_CNTL); RREG32_SMC 507 drivers/gpu/drm/radeon/trinity_dpm.c if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) RREG32_SMC 508 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); RREG32_SMC 523 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(PM_I_CNTL_1); RREG32_SMC 528 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_S_PG_CNTL); RREG32_SMC 533 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_S_PG_CNTL); RREG32_SMC 537 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(PM_I_CNTL_1); RREG32_SMC 597 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); RREG32_SMC 607 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); RREG32_SMC 619 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); RREG32_SMC 631 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); RREG32_SMC 644 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); RREG32_SMC 649 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); RREG32_SMC 661 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); RREG32_SMC 673 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); RREG32_SMC 685 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); RREG32_SMC 697 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); RREG32_SMC 709 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix); RREG32_SMC 740 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); RREG32_SMC 749 drivers/gpu/drm/radeon/trinity_dpm.c if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1)) RREG32_SMC 757 drivers/gpu/drm/radeon/trinity_dpm.c u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL); RREG32_SMC 796 drivers/gpu/drm/radeon/trinity_dpm.c sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL); RREG32_SMC 886 drivers/gpu/drm/radeon/trinity_dpm.c u32 tp = RREG32_SMC(PM_TP); RREG32_SMC 1009 drivers/gpu/drm/radeon/trinity_dpm.c u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT); RREG32_SMC 1019 drivers/gpu/drm/radeon/trinity_dpm.c u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL); RREG32_SMC 1029 drivers/gpu/drm/radeon/trinity_dpm.c u32 tp = RREG32_SMC(PM_TP); RREG32_SMC 1038 drivers/gpu/drm/radeon/trinity_dpm.c value = RREG32_SMC(PM_I_CNTL_1); RREG32_SMC 1181 drivers/gpu/drm/radeon/trinity_dpm.c (RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT; RREG32_SMC 1192 drivers/gpu/drm/radeon/trinity_dpm.c nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG); RREG32_SMC 1314 drivers/gpu/drm/radeon/trinity_dpm.c u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0; RREG32_SMC 1643 drivers/gpu/drm/radeon/trinity_dpm.c (RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;