RREG32_RCU 3456 drivers/gpu/drm/radeon/evergreen.c efuse_straps_4 = RREG32_RCU(0x204); RREG32_RCU 3457 drivers/gpu/drm/radeon/evergreen.c efuse_straps_3 = RREG32_RCU(0x203); RREG32_RCU 192 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); RREG32_RCU 202 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); RREG32_RCU 207 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); RREG32_RCU 212 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4); RREG32_RCU 222 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); RREG32_RCU 233 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); RREG32_RCU 238 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); RREG32_RCU 246 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL); RREG32_RCU 260 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2); RREG32_RCU 265 drivers/gpu/drm/radeon/sumo_dpm.c rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3); RREG32_RCU 149 drivers/gpu/drm/radeon/sumo_smc.c unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK) RREG32_RCU 201 drivers/gpu/drm/radeon/sumo_smc.c sclk_dpm_tdp_limit = RREG32_RCU(regoffset); RREG32_RCU 209 drivers/gpu/drm/radeon/sumo_smc.c u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE); RREG32_RCU 218 drivers/gpu/drm/radeon/sumo_smc.c return RREG32_RCU(RCU_FW_VERSION);