RREG32_PLL 1100 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32_PLL(reg); \ RREG32_PLL 380 drivers/gpu/drm/radeon/r100.c sclk_cntl = RREG32_PLL(SCLK_CNTL); RREG32_PLL 381 drivers/gpu/drm/radeon/r100.c sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); RREG32_PLL 383 drivers/gpu/drm/radeon/r100.c sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); RREG32_PLL 2690 drivers/gpu/drm/radeon/r100.c tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); RREG32_PLL 3883 drivers/gpu/drm/radeon/r100.c tmp = RREG32_PLL(R_00000D_SCLK_CNTL); RREG32_PLL 1371 drivers/gpu/drm/radeon/r300.c tmp = RREG32_PLL(R_00000D_SCLK_CNTL); RREG32_PLL 204 drivers/gpu/drm/radeon/r420.c sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); RREG32_PLL 2553 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_PLL(reg); \ RREG32_PLL 44 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); RREG32_PLL 50 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; RREG32_PLL 57 drivers/gpu/drm/radeon/radeon_clocks.c post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; RREG32_PLL 74 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); RREG32_PLL 80 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; RREG32_PLL 87 drivers/gpu/drm/radeon/radeon_clocks.c post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; RREG32_PLL 121 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; RREG32_PLL 151 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RREG32_PLL 199 drivers/gpu/drm/radeon/radeon_clocks.c u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); RREG32_PLL 215 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RREG32_PLL 241 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; RREG32_PLL 267 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RREG32_PLL 359 drivers/gpu/drm/radeon/radeon_clocks.c RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RREG32_PLL 399 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); RREG32_PLL 403 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 409 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SPLL_CNTL); RREG32_PLL 415 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SPLL_CNTL); RREG32_PLL 421 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); RREG32_PLL 427 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SPLL_CNTL); RREG32_PLL 435 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SPLL_CNTL); RREG32_PLL 441 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SPLL_CNTL); RREG32_PLL 447 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 468 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); RREG32_PLL 481 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 499 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 520 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 525 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 530 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 546 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(R300_SCLK_CNTL2); RREG32_PLL 555 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 573 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 578 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 583 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 599 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_MCLK_MISC); RREG32_PLL 604 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_MCLK_CNTL); RREG32_PLL 619 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_MCLK_CNTL); RREG32_PLL 636 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 642 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(R300_SCLK_CNTL2); RREG32_PLL 649 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); RREG32_PLL 660 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); RREG32_PLL 668 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 691 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 712 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); RREG32_PLL 719 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 731 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 741 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 752 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 763 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 767 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 773 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 791 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(R300_SCLK_CNTL2); RREG32_PLL 796 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 807 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 811 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_MCLK_CNTL); RREG32_PLL 818 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 824 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 841 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_CNTL); RREG32_PLL 872 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(R300_SCLK_CNTL2); RREG32_PLL 881 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_MCLK_CNTL); RREG32_PLL 891 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); RREG32_PLL 897 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 909 drivers/gpu/drm/radeon/radeon_clocks.c tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 1150 drivers/gpu/drm/radeon/radeon_combios.c ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); RREG32_PLL 1155 drivers/gpu/drm/radeon/radeon_combios.c RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; RREG32_PLL 2991 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32_PLL(reg); RREG32_PLL 3070 drivers/gpu/drm/radeon/radeon_combios.c (RREG32_PLL RREG32_PLL 3120 drivers/gpu/drm/radeon/radeon_combios.c tmp = RREG32_PLL(addr); RREG32_PLL 3138 drivers/gpu/drm/radeon/radeon_combios.c (RREG32_PLL RREG32_PLL 3146 drivers/gpu/drm/radeon/radeon_combios.c if (RREG32_PLL RREG32_PLL 3154 drivers/gpu/drm/radeon/radeon_combios.c RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); RREG32_PLL 3158 drivers/gpu/drm/radeon/radeon_combios.c RREG32_PLL RREG32_PLL 224 drivers/gpu/drm/radeon/radeon_legacy_crtc.c RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); RREG32_PLL 232 drivers/gpu/drm/radeon/radeon_legacy_crtc.c while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); RREG32_PLL 251 drivers/gpu/drm/radeon/radeon_legacy_crtc.c RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); RREG32_PLL 259 drivers/gpu/drm/radeon/radeon_legacy_crtc.c while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); RREG32_PLL 854 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & RREG32_PLL 903 drivers/gpu/drm/radeon/radeon_legacy_crtc.c RREG32_PLL(RADEON_P2PLL_CNTL)); RREG32_PLL 922 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 934 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && RREG32_PLL 935 drivers/gpu/drm/radeon/radeon_legacy_crtc.c (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & RREG32_PLL 1009 drivers/gpu/drm/radeon/radeon_legacy_crtc.c RREG32_PLL(RADEON_PPLL_CNTL)); RREG32_PLL 117 drivers/gpu/drm/radeon/radeon_legacy_encoders.c pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 660 drivers/gpu/drm/radeon/radeon_legacy_encoders.c vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); RREG32_PLL 1583 drivers/gpu/drm/radeon/radeon_legacy_encoders.c pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); RREG32_PLL 286 drivers/gpu/drm/radeon/radeon_legacy_tv.c save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); RREG32_PLL 253 drivers/gpu/drm/radeon/rs600.c dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); RREG32_PLL 270 drivers/gpu/drm/radeon/rs600.c dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); RREG32_PLL 282 drivers/gpu/drm/radeon/rs600.c hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); RREG32_PLL 290 drivers/gpu/drm/radeon/rs600.c mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); RREG32_PLL 297 drivers/gpu/drm/radeon/rs600.c dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); RREG32_PLL 510 drivers/gpu/drm/radeon/rv515.c RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); RREG32_PLL 512 drivers/gpu/drm/radeon/rv515.c RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); RREG32_PLL 514 drivers/gpu/drm/radeon/rv515.c RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));