RREG32_NO_KIQ     146 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 		*p++ = RREG32_NO_KIQ(mmMM_DATA);
RREG32_NO_KIQ    1572 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 			value = RREG32_NO_KIQ(mmMM_DATA);
RREG32_NO_KIQ    2184 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 		value = RREG32_NO_KIQ(mmMM_DATA);
RREG32_NO_KIQ      35 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 	return RREG32_NO_KIQ(0xc040) == 0xffffffff;
RREG32_NO_KIQ     252 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
RREG32_NO_KIQ     269 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
RREG32_NO_KIQ     273 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
RREG32_NO_KIQ     525 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
RREG32_NO_KIQ     542 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
RREG32_NO_KIQ     545 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
RREG32_NO_KIQ      56 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
RREG32_NO_KIQ      66 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
RREG32_NO_KIQ     138 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
RREG32_NO_KIQ     186 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c                 val = RREG32_NO_KIQ(
RREG32_NO_KIQ     256 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
RREG32_NO_KIQ     303 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
RREG32_NO_KIQ     356 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
RREG32_NO_KIQ     323 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     328 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     337 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 		reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     345 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     356 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
RREG32_NO_KIQ     372 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 		reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     377 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
RREG32_NO_KIQ     393 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     403 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 		reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
RREG32_NO_KIQ     502 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
RREG32_NO_KIQ     532 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
RREG32_NO_KIQ     221 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	wptr = RREG32_NO_KIQ(reg);
RREG32_NO_KIQ     237 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = RREG32_NO_KIQ(reg);
RREG32_NO_KIQ     394 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	wptr = RREG32_NO_KIQ(reg);
RREG32_NO_KIQ     419 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = RREG32_NO_KIQ(reg);
RREG32_NO_KIQ     494 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		v = RREG32_NO_KIQ(reg_rptr);
RREG32_NO_KIQ      92 drivers/gpu/drm/amd/amdgpu/vi.c 	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
RREG32_NO_KIQ      93 drivers/gpu/drm/amd/amdgpu/vi.c 	r = RREG32_NO_KIQ(mmPCIE_DATA);
RREG32_NO_KIQ     104 drivers/gpu/drm/amd/amdgpu/vi.c 	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
RREG32_NO_KIQ     106 drivers/gpu/drm/amd/amdgpu/vi.c 	(void)RREG32_NO_KIQ(mmPCIE_DATA);
RREG32_NO_KIQ     117 drivers/gpu/drm/amd/amdgpu/vi.c 	r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);