RREG32_MC 43 drivers/gpu/drm/radeon/r520.c tmp = RREG32_MC(R520_MC_STATUS); RREG32_MC 99 drivers/gpu/drm/radeon/r520.c tmp = RREG32_MC(R520_MC_CNTL0); RREG32_MC 1484 drivers/gpu/drm/radeon/r600.c h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); RREG32_MC 1485 drivers/gpu/drm/radeon/r600.c l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); RREG32_MC 72 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); RREG32_MC 117 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); RREG32_MC 181 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_MC_MISC_CNTL); RREG32_MC 185 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_MC_MISC_CNTL); RREG32_MC 203 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); RREG32_MC 321 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); RREG32_MC 324 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); RREG32_MC 326 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); RREG32_MC 328 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); RREG32_MC 330 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); RREG32_MC 342 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_GART_BASE); RREG32_MC 344 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_GART_FEATURE_ID); RREG32_MC 346 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_AGP_MODE_CNTL); RREG32_MC 348 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_MC_MISC_CNTL); RREG32_MC 350 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x5F); RREG32_MC 352 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); RREG32_MC 354 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); RREG32_MC 356 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x3B); RREG32_MC 358 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x3C); RREG32_MC 360 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x30); RREG32_MC 362 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x31); RREG32_MC 364 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x32); RREG32_MC 366 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x33); RREG32_MC 368 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x34); RREG32_MC 370 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x35); RREG32_MC 372 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x36); RREG32_MC 374 drivers/gpu/drm/radeon/rs400.c tmp = RREG32_MC(0x37); RREG32_MC 525 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000100_MC_PT0_CNTL); RREG32_MC 529 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000100_MC_PT0_CNTL); RREG32_MC 533 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000100_MC_PT0_CNTL); RREG32_MC 536 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000100_MC_PT0_CNTL); RREG32_MC 608 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000100_MC_PT0_CNTL); RREG32_MC 610 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000009_MC_CNTL1); RREG32_MC 626 drivers/gpu/drm/radeon/rs600.c tmp = RREG32_MC(R_000009_MC_CNTL1); RREG32_MC 858 drivers/gpu/drm/radeon/rs600.c if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) RREG32_MC 885 drivers/gpu/drm/radeon/rs600.c base = RREG32_MC(R_000004_MC_FB_LOCATION); RREG32_MC 44 drivers/gpu/drm/radeon/rs690.c tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); RREG32_MC 164 drivers/gpu/drm/radeon/rs690.c base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); RREG32_MC 180 drivers/gpu/drm/radeon/rs690.c h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL)); RREG32_MC 181 drivers/gpu/drm/radeon/rs690.c l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION); RREG32_MC 610 drivers/gpu/drm/radeon/rs690.c tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); RREG32_MC 142 drivers/gpu/drm/radeon/rv515.c tmp = RREG32_MC(MC_STATUS); RREG32_MC 186 drivers/gpu/drm/radeon/rv515.c tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; RREG32_MC 1298 drivers/gpu/drm/radeon/rv515.c tmp = RREG32_MC(MC_MISC_LAT_TIMER);