RREG32_ENDPOINT 37 drivers/gpu/drm/radeon/dce3_1_afmt.c tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); RREG32_ENDPOINT 55 drivers/gpu/drm/radeon/dce3_1_afmt.c tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); RREG32_ENDPOINT 68 drivers/gpu/drm/radeon/dce6_afmt.c tmp = RREG32_ENDPOINT(offset, RREG32_ENDPOINT 164 drivers/gpu/drm/radeon/dce6_afmt.c tmp = RREG32_ENDPOINT(dig->pin->offset, RREG32_ENDPOINT 189 drivers/gpu/drm/radeon/dce6_afmt.c tmp = RREG32_ENDPOINT(dig->pin->offset, RREG32_ENDPOINT 126 drivers/gpu/drm/radeon/evergreen_hdmi.c tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); RREG32_ENDPOINT 144 drivers/gpu/drm/radeon/evergreen_hdmi.c tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);