RREG32 1091 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32(reg); \ RREG32 1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) RREG32 1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) RREG32 59 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c (*dump)[i++][1] = RREG32(addr); \ RREG32 152 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 159 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c data = RREG32(sdmax_gfx_context_cntl); RREG32 245 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 266 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 271 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 281 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | RREG32 284 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); RREG32 286 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); RREG32 265 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c while (!(RREG32(SOC15_REG_OFFSET( RREG32 381 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); RREG32 465 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c (*dump)[i++][1] = RREG32(addr); \ RREG32 510 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 517 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c data = RREG32(sdmax_gfx_context_cntl); RREG32 604 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); RREG32 609 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && RREG32 610 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) RREG32 628 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 680 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(mmCP_HQD_IQ_TIMER); RREG32 709 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); RREG32 729 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); RREG32 757 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 762 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 772 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | RREG32 775 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); RREG32 777 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); RREG32 788 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) RREG32 799 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) RREG32 277 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) RREG32 385 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c (*dump)[i++][1] = RREG32(addr); \ RREG32 427 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 435 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); RREG32 440 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); RREG32 510 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c act = RREG32(mmCP_HQD_ACTIVE); RREG32 515 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (low == RREG32(mmCP_HQD_PQ_BASE) && RREG32 516 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c high == RREG32(mmCP_HQD_PQ_BASE_HI)) RREG32 533 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 580 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c temp = RREG32(mmCP_HQD_IQ_TIMER); RREG32 609 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); RREG32 628 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c temp = RREG32(mmCP_HQD_ACTIVE); RREG32 655 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 660 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 670 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | RREG32 673 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); RREG32 767 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 777 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 817 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 821 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c RREG32(mmVM_INVALIDATE_RESPONSE); RREG32 839 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c RREG32(mmVM_INVALIDATE_RESPONSE); RREG32 854 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 234 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) RREG32 308 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c value = RREG32(mmRLC_CP_SCHEDULERS); RREG32 370 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c (*dump)[i++][1] = RREG32(addr); \ RREG32 411 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 419 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); RREG32 424 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); RREG32 503 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c act = RREG32(mmCP_HQD_ACTIVE); RREG32 508 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (low == RREG32(mmCP_HQD_PQ_BASE) && RREG32 509 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c high == RREG32(mmCP_HQD_PQ_BASE_HI)) RREG32 526 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 576 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c temp = RREG32(mmCP_HQD_IQ_TIMER); RREG32 605 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); RREG32 624 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c temp = RREG32(mmCP_HQD_ACTIVE); RREG32 651 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 656 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 666 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | RREG32 669 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); RREG32 680 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 690 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 776 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); RREG32 780 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c RREG32(mmVM_INVALIDATE_RESPONSE); RREG32 798 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c RREG32(mmVM_INVALIDATE_RESPONSE); RREG32 172 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c while (!(RREG32(SOC15_REG_OFFSET( RREG32 189 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c while (!(RREG32(SOC15_REG_OFFSET( RREG32 282 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); RREG32 365 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c (*dump)[i++][1] = RREG32(addr); \ RREG32 409 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 416 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c data = RREG32(sdmax_gfx_context_cntl); RREG32 500 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); RREG32 505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && RREG32 506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) RREG32 524 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 567 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); RREG32 595 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); RREG32 600 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); RREG32 610 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | RREG32 613 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); RREG32 615 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); RREG32 626 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) RREG32 637 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) RREG32 1675 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); RREG32 1694 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2); RREG32 1695 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); RREG32 1713 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3); RREG32 1725 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7); RREG32 1904 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c r = RREG32(reg); RREG32 47 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c return RREG32(offset); RREG32 166 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c value = RREG32(*pos >> 2); RREG32 554 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c tmp = RREG32(reg); RREG32 138 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; RREG32 51 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 57 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; RREG32 60 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; RREG32 64 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; RREG32 67 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; RREG32 71 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; RREG32 73 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 75 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; RREG32 77 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_data_reg); RREG32 90 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; RREG32 92 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 94 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; RREG32 96 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_data_reg); RREG32 109 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->y_clk_reg); RREG32 124 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->y_data_reg); RREG32 138 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; RREG32 151 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; RREG32 117 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c val = RREG32(reg_index); RREG32 25 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h #define RREG64_UMC(reg) (RREG32(reg) | \ RREG32 26 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h ((uint64_t)RREG32((reg) + 1) << 32)) RREG32 395 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); RREG32 727 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); RREG32 801 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch); RREG32 46 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); RREG32 60 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); RREG32 1764 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); RREG32 1809 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); RREG32 1857 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); RREG32 1858 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_3_scratch = RREG32(mmBIOS_SCRATCH_3); RREG32 1859 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); RREG32 83 drivers/gpu/drm/amd/amdgpu/cik.c (void)RREG32(mmPCIE_INDEX); RREG32 84 drivers/gpu/drm/amd/amdgpu/cik.c r = RREG32(mmPCIE_DATA); RREG32 95 drivers/gpu/drm/amd/amdgpu/cik.c (void)RREG32(mmPCIE_INDEX); RREG32 97 drivers/gpu/drm/amd/amdgpu/cik.c (void)RREG32(mmPCIE_DATA); RREG32 108 drivers/gpu/drm/amd/amdgpu/cik.c r = RREG32(mmSMC_IND_DATA_0); RREG32 130 drivers/gpu/drm/amd/amdgpu/cik.c r = RREG32(mmUVD_CTX_DATA); RREG32 152 drivers/gpu/drm/amd/amdgpu/cik.c r = RREG32(mmDIDT_IND_DATA); RREG32 883 drivers/gpu/drm/amd/amdgpu/cik.c tmp = RREG32(mmCONFIG_CNTL); RREG32 900 drivers/gpu/drm/amd/amdgpu/cik.c bus_cntl = RREG32(mmBUS_CNTL); RREG32 902 drivers/gpu/drm/amd/amdgpu/cik.c d1vga_control = RREG32(mmD1VGA_CONTROL); RREG32 903 drivers/gpu/drm/amd/amdgpu/cik.c d2vga_control = RREG32(mmD2VGA_CONTROL); RREG32 904 drivers/gpu/drm/amd/amdgpu/cik.c vga_render_control = RREG32(mmVGA_RENDER_CONTROL); RREG32 961 drivers/gpu/drm/amd/amdgpu/cik.c dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); RREG32 1051 drivers/gpu/drm/amd/amdgpu/cik.c val = RREG32(reg_offset); RREG32 1118 drivers/gpu/drm/amd/amdgpu/cik.c return RREG32(reg_offset); RREG32 1151 drivers/gpu/drm/amd/amdgpu/cik.c save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); RREG32 1152 drivers/gpu/drm/amd/amdgpu/cik.c save->gmcon_misc = RREG32(mmGMCON_MISC); RREG32 1153 drivers/gpu/drm/amd/amdgpu/cik.c save->gmcon_misc3 = RREG32(mmGMCON_MISC3); RREG32 1255 drivers/gpu/drm/amd/amdgpu/cik.c if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { RREG32 1302 drivers/gpu/drm/amd/amdgpu/cik.c return RREG32(mmCONFIG_MEMSIZE); RREG32 1714 drivers/gpu/drm/amd/amdgpu/cik.c return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) RREG32 1728 drivers/gpu/drm/amd/amdgpu/cik.c RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); RREG32 1739 drivers/gpu/drm/amd/amdgpu/cik.c RREG32(mmHDP_DEBUG0); RREG32 62 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 63 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 81 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 82 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 117 drivers/gpu/drm/amd/amdgpu/cik_ih.c interrupt_cntl = RREG32(mmINTERRUPT_CNTL); RREG32 203 drivers/gpu/drm/amd/amdgpu/cik_ih.c tmp = RREG32(mmIH_RB_CNTL); RREG32 355 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 371 drivers/gpu/drm/amd/amdgpu/cik_ih.c tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; RREG32 384 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 390 drivers/gpu/drm/amd/amdgpu/cik_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 394 drivers/gpu/drm/amd/amdgpu/cik_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 400 drivers/gpu/drm/amd/amdgpu/cik_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 183 drivers/gpu/drm/amd/amdgpu/cik_sdma.c return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; RREG32 318 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); RREG32 377 drivers/gpu/drm/amd/amdgpu/cik_sdma.c f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); RREG32 415 drivers/gpu/drm/amd/amdgpu/cik_sdma.c me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); RREG32 891 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); RREG32 896 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); RREG32 909 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); RREG32 914 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); RREG32 919 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); RREG32 924 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1044 drivers/gpu/drm/amd/amdgpu/cik_sdma.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 1060 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | RREG32 1074 drivers/gpu/drm/amd/amdgpu/cik_sdma.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 1078 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1085 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1092 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1096 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1102 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1122 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1127 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1138 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1143 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 62 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 63 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 81 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 82 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 117 drivers/gpu/drm/amd/amdgpu/cz_ih.c interrupt_cntl = RREG32(mmINTERRUPT_CNTL); RREG32 148 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = RREG32(mmIH_CNTL); RREG32 205 drivers/gpu/drm/amd/amdgpu/cz_ih.c tmp = RREG32(mmIH_RB_CNTL); RREG32 334 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 350 drivers/gpu/drm/amd/amdgpu/cz_ih.c tmp = RREG32(mmSRBM_STATUS); RREG32 362 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 369 drivers/gpu/drm/amd/amdgpu/cz_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 373 drivers/gpu/drm/amd/amdgpu/cz_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 379 drivers/gpu/drm/amd/amdgpu/cz_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 182 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); RREG32 204 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); RREG32 243 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 257 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); RREG32 266 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); RREG32 267 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 289 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & RREG32 313 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 348 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 354 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 358 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 393 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 414 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 416 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 424 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 443 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 451 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), RREG32 489 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 622 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); RREG32 626 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); RREG32 631 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); RREG32 664 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 1119 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1122 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1129 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); RREG32 1474 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); RREG32 1477 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); RREG32 1481 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); RREG32 1484 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); RREG32 1488 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); RREG32 1491 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); RREG32 1539 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); RREG32 1583 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); RREG32 1589 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); RREG32 1616 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); RREG32 1622 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1629 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1634 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1641 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1648 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1653 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); RREG32 1666 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); RREG32 1670 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); RREG32 1674 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); RREG32 1706 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1713 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1717 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1810 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; RREG32 2003 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2024 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); RREG32 2084 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); RREG32 2103 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2108 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2112 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2116 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2145 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2151 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2156 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2161 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2171 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2274 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); RREG32 2934 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2938 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2944 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2965 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 2971 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 2994 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3000 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3024 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3029 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3100 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); RREG32 3128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & RREG32 3174 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3189 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); RREG32 3204 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); RREG32 3214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); RREG32 3260 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); RREG32 200 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); RREG32 222 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); RREG32 261 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 275 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); RREG32 284 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); RREG32 285 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 307 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & RREG32 331 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 366 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 372 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 376 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 410 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 430 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 432 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 440 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 459 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 467 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 511 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), RREG32 515 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 648 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); RREG32 652 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); RREG32 657 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); RREG32 690 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 1145 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1148 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1240 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); RREG32 1516 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); RREG32 1519 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); RREG32 1523 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); RREG32 1526 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); RREG32 1530 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); RREG32 1533 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); RREG32 1581 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); RREG32 1625 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); RREG32 1631 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); RREG32 1658 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); RREG32 1664 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1671 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1676 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1683 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1690 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1695 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); RREG32 1708 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); RREG32 1712 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); RREG32 1716 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); RREG32 1748 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1755 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1759 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1852 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; RREG32 2045 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2066 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); RREG32 2126 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); RREG32 2145 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2149 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2153 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2181 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2187 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2191 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2195 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2204 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); RREG32 2353 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); RREG32 3060 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 3064 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 3070 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 3091 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3097 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3120 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3126 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); RREG32 3150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3226 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); RREG32 3254 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & RREG32 3300 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); RREG32 3315 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); RREG32 3330 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); RREG32 3340 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); RREG32 3387 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); RREG32 133 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); RREG32 156 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); RREG32 209 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); RREG32 217 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); RREG32 218 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 241 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) RREG32 264 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); RREG32 292 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 303 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 335 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 353 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); RREG32 382 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & RREG32 386 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 463 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 952 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); RREG32 961 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); RREG32 1023 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & RREG32 1383 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); RREG32 1400 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); RREG32 1406 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); RREG32 1409 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); RREG32 1413 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); RREG32 1416 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); RREG32 1420 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); RREG32 1423 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); RREG32 1464 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1485 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); RREG32 1513 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1517 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); RREG32 1521 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); RREG32 1525 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); RREG32 1534 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); RREG32 1538 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1543 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1557 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_GC + dig->afmt->offset); RREG32 1571 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1578 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); RREG32 1582 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1586 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); RREG32 1593 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1608 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); RREG32 1612 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); RREG32 1616 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); RREG32 1774 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; RREG32 2164 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); RREG32 2829 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c interrupt_mask = RREG32(mmINT_MASK + reg_block); RREG32 2834 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c interrupt_mask = RREG32(mmINT_MASK + reg_block); RREG32 2864 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); RREG32 2869 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); RREG32 2933 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); RREG32 2977 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); RREG32 3005 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & RREG32 3054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); RREG32 3058 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); RREG32 130 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); RREG32 152 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); RREG32 202 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); RREG32 211 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); RREG32 212 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 234 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & RREG32 258 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); RREG32 286 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 297 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 328 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); RREG32 348 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { RREG32 349 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 357 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 376 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 384 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 425 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), RREG32 429 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); RREG32 566 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & RREG32 599 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 1054 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1063 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); RREG32 1537 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c val = RREG32(mmHDMI_CONTROL + offset); RREG32 1739 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; RREG32 2177 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); RREG32 2822 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2826 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2832 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 2877 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); RREG32 2882 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); RREG32 2928 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); RREG32 2933 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); RREG32 2956 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); RREG32 2961 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); RREG32 3025 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); RREG32 3069 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); RREG32 3097 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & RREG32 3146 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); RREG32 3150 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); RREG32 110 drivers/gpu/drm/amd/amdgpu/df_v3_6.c ficadl_val = RREG32(data); RREG32 113 drivers/gpu/drm/amd/amdgpu/df_v3_6.c ficadh_val = RREG32(data); RREG32 158 drivers/gpu/drm/amd/amdgpu/df_v3_6.c *lo_val = RREG32(data); RREG32 160 drivers/gpu/drm/amd/amdgpu/df_v3_6.c *hi_val = RREG32(data); RREG32 463 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(scratch); RREG32 531 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(scratch); RREG32 1890 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); RREG32 4879 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_int_cntl = RREG32(cp_int_cntl_reg); RREG32 4885 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_int_cntl = RREG32(cp_int_cntl_reg); RREG32 4932 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 4938 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 5136 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(target); RREG32 5146 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(target); RREG32 1330 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data = RREG32(mmCC_RB_BACKEND_DISABLE) | RREG32 1331 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 1506 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmCC_RB_BACKEND_DISABLE); RREG32 1508 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 1510 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmPA_SC_RASTER_CONFIG); RREG32 1535 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | RREG32 1536 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); RREG32 1553 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); RREG32 1681 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); RREG32 1682 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); RREG32 1741 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c sx_debug_1 = RREG32(mmSX_DEBUG_1); RREG32 1773 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 1814 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(scratch); RREG32 1938 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(scratch); RREG32 2154 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return RREG32(mmCP_RB0_WPTR); RREG32 2156 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return RREG32(mmCP_RB1_WPTR); RREG32 2158 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return RREG32(mmCP_RB2_WPTR); RREG32 2168 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (void)RREG32(mmCP_RB0_WPTR); RREG32 2177 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (void)RREG32(mmCP_RB1_WPTR); RREG32 2180 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (void)RREG32(mmCP_RB2_WPTR); RREG32 2260 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 tmp = RREG32(mmCP_INT_CNTL_RING0); RREG32 2274 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(mmDB_DEPTH_INFO); RREG32 2278 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) RREG32 2445 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) RREG32 2451 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) RREG32 2461 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(mmRLC_CNTL); RREG32 2470 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_CNTL); RREG32 2512 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(mmMC_SEQ_MISC0); RREG32 2571 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); RREG32 2593 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 2594 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 2595 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 2596 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 2612 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 2618 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 2624 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 2637 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 2642 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 2647 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 2691 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 2780 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (void)RREG32(mmDB_RENDER_CONTROL); RREG32 2790 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(mmRLC_MAX_PG_CU); RREG32 2801 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 2815 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 2832 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c tmp = RREG32(mmRLC_AUTO_PG_CTRL); RREG32 2971 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | RREG32 2972 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 2994 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return RREG32(mmSQ_IND_DATA); RREG32 3009 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c *(out++) = RREG32(mmSQ_IND_DATA); RREG32 3212 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) RREG32 3243 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 3248 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 3265 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); RREG32 3270 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); RREG32 3278 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); RREG32 3283 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); RREG32 3306 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 3311 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 3331 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 3336 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 1625 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmCC_RB_BACKEND_DISABLE); RREG32 1626 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 1831 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCC_RB_BACKEND_DISABLE); RREG32 1833 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 1835 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmPA_SC_RASTER_CONFIG); RREG32 1837 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmPA_SC_RASTER_CONFIG_1); RREG32 1995 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSPI_CONFIG_CNTL); RREG32 2003 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; RREG32 2007 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; RREG32 2011 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; RREG32 2044 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSPI_ARB_PRIORITY); RREG32 2110 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(scratch); RREG32 2387 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(scratch); RREG32 2667 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c return RREG32(mmCP_RB0_WPTR); RREG32 2675 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c (void)RREG32(mmCP_RB0_WPTR); RREG32 2895 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmCP_HPD_EOP_CONTROL); RREG32 2909 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (RREG32(mmCP_HQD_ACTIVE) & 1) { RREG32 2912 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) RREG32 2947 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32 2958 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); RREG32 2967 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); RREG32 3002 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32 3021 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); RREG32 3027 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); RREG32 3028 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); RREG32 3029 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); RREG32 3030 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); RREG32 3031 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); RREG32 3032 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); RREG32 3033 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); RREG32 3034 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); RREG32 3035 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); RREG32 3036 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); RREG32 3037 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); RREG32 3038 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); RREG32 3039 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); RREG32 3040 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); RREG32 3041 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); RREG32 3042 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); RREG32 3058 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); RREG32 3119 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmCP_CPF_DEBUG); RREG32 3170 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 tmp = RREG32(mmCP_INT_CNTL_RING0); RREG32 3356 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmRLC_LB_CNTL); RREG32 3374 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) RREG32 3388 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) RREG32 3398 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmRLC_CNTL); RREG32 3407 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_CNTL); RREG32 3416 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) RREG32 3442 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) RREG32 3448 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) RREG32 3496 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 3534 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; RREG32 3577 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); RREG32 3603 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 3604 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 3605 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 3606 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 3623 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 3630 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 3650 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 3665 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 3670 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmRLC_MEM_SLP_CNTL); RREG32 3676 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 3682 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 3721 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3735 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3748 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3761 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3784 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3789 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_AUTO_PG_CTRL); RREG32 3794 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3799 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_AUTO_PG_CTRL); RREG32 3804 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmDB_RENDER_CONTROL); RREG32 3826 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); RREG32 3827 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); RREG32 3843 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmRLC_MAX_PG_CU); RREG32 3854 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3868 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3901 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c orig = data = RREG32(mmRLC_PG_CNTL); RREG32 3909 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmCP_RB_WPTR_POLL_CNTL); RREG32 3917 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmRLC_PG_DELAY_2); RREG32 3922 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c data = RREG32(mmRLC_AUTO_PG_CTRL); RREG32 4084 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | RREG32 4085 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 4148 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c return RREG32(mmSQ_IND_DATA); RREG32 4163 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c *(out++) = RREG32(mmSQ_IND_DATA); RREG32 4338 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); RREG32 4339 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); RREG32 4346 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); RREG32 4350 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); RREG32 4600 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) RREG32 4614 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; RREG32 4630 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_STATUS); RREG32 4646 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_STATUS2); RREG32 4651 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSRBM_STATUS); RREG32 4670 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 4674 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 4680 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 4684 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 4688 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 4694 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 4709 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 4714 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 4760 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 4765 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 4783 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 4788 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 4808 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 4813 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); RREG32 5099 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); RREG32 5102 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); RREG32 859 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(scratch); RREG32 1565 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGB_EDC_MODE); RREG32 1694 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCC_GC_EDC_CONFIG); RREG32 1701 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(sec_ded_counter_registers[i]); RREG32 1853 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); RREG32 1854 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); RREG32 1861 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); RREG32 1865 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); RREG32 3481 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmCC_RB_BACKEND_DISABLE) | RREG32 3482 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 3686 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmCC_RB_BACKEND_DISABLE); RREG32 3688 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmGC_USER_RB_BACKEND_DISABLE); RREG32 3690 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmPA_SC_RASTER_CONFIG); RREG32 3692 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmPA_SC_RASTER_CONFIG_1); RREG32 3856 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmSPI_ARB_PRIORITY); RREG32 3877 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) RREG32 3899 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) RREG32 3908 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 tmp = RREG32(mmCP_INT_CNTL_RING0); RREG32 4148 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 tmp = RREG32(mmCP_ME_CNTL); RREG32 4264 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); RREG32 4367 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmRLC_CP_SCHEDULERS); RREG32 4440 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { RREG32 4443 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) RREG32 4480 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_EOP_CONTROL); RREG32 4487 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL), RREG32 4499 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_MQD_CONTROL); RREG32 4509 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_PQ_CONTROL); RREG32 4537 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); RREG32 4554 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); RREG32 4559 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); RREG32 4564 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_IB_CONTROL); RREG32 4569 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_IQ_TIMER); RREG32 4573 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL); RREG32 4578 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR); RREG32 4579 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR); RREG32 4580 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); RREG32 4581 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); RREG32 4582 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); RREG32 4583 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO); RREG32 4584 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI); RREG32 4585 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET); RREG32 4586 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE); RREG32 4587 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); RREG32 4588 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE); RREG32 4589 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS); RREG32 4590 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR); RREG32 4591 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM); RREG32 4592 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES); RREG32 4887 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) RREG32 4888 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c || RREG32(mmGRBM_STATUS2) != 0x8) RREG32 4898 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (RREG32(mmGRBM_STATUS2) != 0x8) RREG32 4983 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGRBM_STATUS); RREG32 5000 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGRBM_STATUS2); RREG32 5019 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmSRBM_STATUS); RREG32 5093 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGMCON_DEBUG); RREG32 5101 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 5105 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 5111 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGRBM_SOFT_RESET); RREG32 5115 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 5119 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 5125 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 5129 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(mmGMCON_DEBUG); RREG32 5196 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | RREG32 5197 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 5248 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c return RREG32(mmSQ_IND_DATA); RREG32 5263 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c *(out++) = RREG32(mmSQ_IND_DATA); RREG32 5396 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmDB_RENDER_CONTROL); RREG32 5492 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5497 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_CGCG_CGLS_CTRL); RREG32 5506 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 5515 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_MEM_SLP_CNTL); RREG32 5520 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 5535 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_SERDES_WR_CTRL); RREG32 5577 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c rlc_setting = RREG32(mmRLC_CNTL); RREG32 5588 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_CNTL); RREG32 5596 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if ((RREG32(mmRLC_GPM_STAT) & RREG32 5605 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) RREG32 5616 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_CNTL); RREG32 5622 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) RREG32 5661 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5683 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 5702 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5711 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmRLC_MEM_SLP_CNTL); RREG32 5718 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmCP_MEM_SLP_CNTL); RREG32 5725 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp = data = RREG32(mmCGTS_SM_CTRL_REG); RREG32 5751 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL); RREG32 5756 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5780 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5801 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); RREG32 5808 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 5809 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 5810 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 5811 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmCB_CGTT_SCLK_CTRL); RREG32 6054 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c return RREG32(mmCP_RB0_WPTR); RREG32 6067 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c (void)RREG32(mmCP_RB0_WPTR); RREG32 6289 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(reg); RREG32 6581 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 6586 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 6854 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE); RREG32 7096 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); RREG32 7099 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); RREG32 7120 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | RREG32 7121 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); RREG32 862 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32(scratch); RREG32 2675 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); RREG32 2759 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); RREG32 2787 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); RREG32 2800 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); RREG32 2805 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); RREG32 2810 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); RREG32 2827 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2841 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2855 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2868 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2881 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2890 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); RREG32 2898 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 2911 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); RREG32 4384 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i])); RREG32 5168 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32(reg); RREG32 5531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 5537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl = RREG32(mec_int_cntl_reg); RREG32 6124 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c reg_value = RREG32( RREG32 87 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); RREG32 96 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); RREG32 106 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); RREG32 115 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); RREG32 145 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c RREG32(hub->vm_l2_pro_fault_status); RREG32 147 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c status = RREG32(hub->vm_l2_pro_fault_status); RREG32 81 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 100 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 138 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) RREG32 185 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; RREG32 210 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) RREG32 215 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) RREG32 228 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; RREG32 257 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 262 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 289 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmMC_ARB_RAMCFG); RREG32 297 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 330 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 331 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 415 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 446 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_PRT_CNTL); RREG32 822 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 d1vga_control = RREG32(mmD1VGA_CONTROL); RREG32 828 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 viewport = RREG32(mmVIEWPORT_SIZE); RREG32 849 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 tmp = RREG32(mmMC_SEQ_MISC0); RREG32 904 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u64 tmp = RREG32(mmMC_VM_FB_OFFSET); RREG32 988 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1015 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1035 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1039 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1045 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1071 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1074 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1079 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1082 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1099 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 1100 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 96 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 114 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 203 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); RREG32 226 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), RREG32 232 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), RREG32 245 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; RREG32 280 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 285 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 305 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmHDP_MISC_CNTL); RREG32 309 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 332 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmMC_ARB_RAMCFG); RREG32 338 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 372 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 373 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 385 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; RREG32 498 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 529 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_PRT_CNTL); RREG32 599 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); RREG32 607 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_L2_CNTL); RREG32 621 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_L2_CNTL3); RREG32 633 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 663 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 675 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmCHUB_CONTROL); RREG32 720 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); RREG32 726 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_L2_CNTL); RREG32 806 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c orig = data = RREG32(mc_cg_registers[i]); RREG32 823 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c orig = data = RREG32(mc_cg_registers[i]); RREG32 861 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c orig = data = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 877 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c orig = data = RREG32(mmHDP_MEM_POWER_LS); RREG32 942 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 d1vga_control = RREG32(mmD1VGA_CONTROL); RREG32 948 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 viewport = RREG32(mmVIEWPORT_SIZE); RREG32 969 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 tmp = RREG32(mmMC_SEQ_MISC0); RREG32 1033 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u64 tmp = RREG32(mmMC_VM_FB_OFFSET); RREG32 1126 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1143 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | RREG32 1160 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1180 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1184 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1190 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1218 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1222 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1228 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1232 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1249 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 1250 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 1251 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); RREG32 184 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 202 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); RREG32 328 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); RREG32 351 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), RREG32 357 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), RREG32 397 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_SEQ_MISC0); RREG32 421 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_SEQ_MISC0); RREG32 436 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; RREG32 471 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVGA_HDP_CONTROL); RREG32 476 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVGA_RENDER_CONTROL); RREG32 507 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmHDP_MISC_CNTL); RREG32 511 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 534 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_ARB_RAMCFG); RREG32 540 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_SHARED_CHMAP); RREG32 574 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 575 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 587 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; RREG32 723 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 756 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_PRT_CNTL); RREG32 826 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); RREG32 834 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_L2_CNTL); RREG32 843 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_L2_CNTL2); RREG32 849 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_L2_CNTL3); RREG32 855 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_L2_CNTL4); RREG32 876 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 906 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 964 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); RREG32 970 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_L2_CNTL); RREG32 1060 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 d1vga_control = RREG32(mmD1VGA_CONTROL); RREG32 1066 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 viewport = RREG32(mmVIEWPORT_SIZE); RREG32 1093 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_SEQ_MISC0_FIJI); RREG32 1095 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmMC_SEQ_MISC0); RREG32 1159 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u64 tmp = RREG32(mmMC_VM_FB_OFFSET); RREG32 1260 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1277 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | RREG32 1295 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1343 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1347 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1353 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1390 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1394 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1400 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT0_CNTL); RREG32 1404 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c tmp = RREG32(mmVM_CONTEXT1_CNTL); RREG32 1428 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 1429 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 1430 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); RREG32 1489 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_HUB_CG); RREG32 1493 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_SIP_CG); RREG32 1497 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_VM_CG); RREG32 1501 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_XPB_CLK_GAT); RREG32 1505 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmATC_MISC_CG); RREG32 1509 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_WR_CG); RREG32 1513 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_RD_CG); RREG32 1517 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_VM_CG); RREG32 1521 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmVM_L2_CG); RREG32 1525 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_HUB_CG); RREG32 1529 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_SIP_CG); RREG32 1533 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_VM_CG); RREG32 1537 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_XPB_CLK_GAT); RREG32 1541 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmATC_MISC_CG); RREG32 1545 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_WR_CG); RREG32 1549 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_RD_CG); RREG32 1553 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_VM_CG); RREG32 1557 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmVM_L2_CG); RREG32 1569 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_HUB_CG); RREG32 1573 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_SIP_CG); RREG32 1577 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_VM_CG); RREG32 1581 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_XPB_CLK_GAT); RREG32 1585 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmATC_MISC_CG); RREG32 1589 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_WR_CG); RREG32 1593 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_RD_CG); RREG32 1597 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_VM_CG); RREG32 1601 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmVM_L2_CG); RREG32 1605 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_HUB_CG); RREG32 1609 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_SIP_CG); RREG32 1613 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_VM_CG); RREG32 1617 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_XPB_CLK_GAT); RREG32 1621 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmATC_MISC_CG); RREG32 1625 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_WR_CG); RREG32 1629 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_RD_CG); RREG32 1633 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_CITF_MISC_VM_CG); RREG32 1637 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmVM_L2_CG); RREG32 1679 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c data = RREG32(mmMC_HUB_MISC_HUB_CG); RREG32 214 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 220 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 228 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 234 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 306 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 317 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); RREG32 365 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c RREG32(hub->vm_l2_pro_fault_status); RREG32 367 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c status = RREG32(hub->vm_l2_pro_fault_status); RREG32 1505 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); RREG32 62 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 63 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 81 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 82 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); RREG32 117 drivers/gpu/drm/amd/amdgpu/iceland_ih.c interrupt_cntl = RREG32(mmINTERRUPT_CNTL); RREG32 148 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = RREG32(mmIH_CNTL); RREG32 205 drivers/gpu/drm/amd/amdgpu/iceland_ih.c tmp = RREG32(mmIH_RB_CNTL); RREG32 334 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 350 drivers/gpu/drm/amd/amdgpu/iceland_ih.c tmp = RREG32(mmSRBM_STATUS); RREG32 362 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 369 drivers/gpu/drm/amd/amdgpu/iceland_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 373 drivers/gpu/drm/amd/amdgpu/iceland_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 379 drivers/gpu/drm/amd/amdgpu/iceland_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 125 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 v = RREG32(mmDOUT_SCRATCH3); RREG32 432 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data = RREG32(config_regs->offset); RREG32 40 drivers/gpu/drm/amd/amdgpu/kv_smc.c if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0) RREG32 44 drivers/gpu/drm/amd/amdgpu/kv_smc.c tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK; RREG32 101 drivers/gpu/drm/amd/amdgpu/kv_smc.c *value = RREG32(mmSMC_IND_DATA_0); RREG32 142 drivers/gpu/drm/amd/amdgpu/kv_smc.c original_data = RREG32(mmSMC_IND_DATA_0); RREG32 196 drivers/gpu/drm/amd/amdgpu/kv_smc.c original_data = RREG32(mmSMC_IND_DATA_0); RREG32 77 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 doorbell_range = RREG32(reg); RREG32 99 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 doorbell_range = RREG32(reg); RREG32 76 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 doorbell_range = RREG32(reg); RREG32 83 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 doorbell_range = RREG32(reg); RREG32 99 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 doorbell_range = RREG32(reg); RREG32 114 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c doorbell_range = RREG32(reg); RREG32 136 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c doorbell_range = RREG32(reg); RREG32 71 drivers/gpu/drm/amd/amdgpu/nv.c (void)RREG32(address); RREG32 72 drivers/gpu/drm/amd/amdgpu/nv.c r = RREG32(data); RREG32 86 drivers/gpu/drm/amd/amdgpu/nv.c (void)RREG32(address); RREG32 88 drivers/gpu/drm/amd/amdgpu/nv.c (void)RREG32(data); RREG32 102 drivers/gpu/drm/amd/amdgpu/nv.c r = RREG32(data); RREG32 193 drivers/gpu/drm/amd/amdgpu/nv.c val = RREG32(reg_offset); RREG32 210 drivers/gpu/drm/amd/amdgpu/nv.c return RREG32(reg_offset); RREG32 348 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); RREG32 682 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); RREG32 502 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); RREG32 580 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); RREG32 210 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; RREG32 351 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); RREG32 354 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); RREG32 393 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); RREG32 439 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); RREG32 472 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); RREG32 937 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 953 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | RREG32 967 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 971 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); RREG32 978 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); RREG32 985 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 989 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 995 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1015 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1020 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1031 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1036 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; RREG32 525 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); RREG32 528 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); RREG32 586 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); RREG32 628 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); RREG32 677 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); RREG32 704 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); RREG32 722 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); RREG32 740 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); RREG32 1222 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 1238 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | RREG32 1252 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c u32 tmp = RREG32(mmSRBM_STATUS2); RREG32 1319 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1323 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1329 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1349 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1354 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); RREG32 1365 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1370 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); RREG32 1448 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); RREG32 1462 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); RREG32 1487 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); RREG32 1495 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); RREG32 1542 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); RREG32 1547 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); RREG32 79 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) RREG32 1162 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); RREG32 1169 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); RREG32 1181 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); RREG32 1187 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); RREG32 1193 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); RREG32 2226 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); RREG32 2231 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); RREG32 302 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; RREG32 303 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; RREG32 510 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); RREG32 513 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); RREG32 572 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); RREG32 607 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); RREG32 642 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); RREG32 663 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, RREG32 692 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); RREG32 693 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); RREG32 715 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); RREG32 723 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); RREG32 729 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); RREG32 737 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); RREG32 746 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); RREG32 1327 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); RREG32 1343 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); RREG32 1344 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); RREG32 1418 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_cntl = RREG32(reg_offset); RREG32 1484 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); RREG32 1497 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); RREG32 1521 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); RREG32 1528 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); RREG32 1576 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); RREG32 1581 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); RREG32 911 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(AMDGPU_PCIE_INDEX); RREG32 912 drivers/gpu/drm/amd/amdgpu/si.c r = RREG32(AMDGPU_PCIE_DATA); RREG32 923 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(AMDGPU_PCIE_INDEX); RREG32 925 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(AMDGPU_PCIE_DATA); RREG32 936 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(PCIE_PORT_INDEX); RREG32 937 drivers/gpu/drm/amd/amdgpu/si.c r = RREG32(PCIE_PORT_DATA); RREG32 948 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(PCIE_PORT_INDEX); RREG32 950 drivers/gpu/drm/amd/amdgpu/si.c (void)RREG32(PCIE_PORT_DATA); RREG32 961 drivers/gpu/drm/amd/amdgpu/si.c r = RREG32(SMC_IND_DATA_0); RREG32 1039 drivers/gpu/drm/amd/amdgpu/si.c val = RREG32(reg_offset); RREG32 1088 drivers/gpu/drm/amd/amdgpu/si.c return RREG32(reg_offset); RREG32 1120 drivers/gpu/drm/amd/amdgpu/si.c bus_cntl = RREG32(R600_BUS_CNTL); RREG32 1122 drivers/gpu/drm/amd/amdgpu/si.c d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); RREG32 1123 drivers/gpu/drm/amd/amdgpu/si.c d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); RREG32 1124 drivers/gpu/drm/amd/amdgpu/si.c vga_render_control = RREG32(VGA_RENDER_CONTROL); RREG32 1126 drivers/gpu/drm/amd/amdgpu/si.c rom_cntl = RREG32(R600_ROM_CNTL); RREG32 1178 drivers/gpu/drm/amd/amdgpu/si.c dw_ptr[i] = RREG32(mmROM_DATA); RREG32 1197 drivers/gpu/drm/amd/amdgpu/si.c return RREG32(mmCONFIG_MEMSIZE); RREG32 1204 drivers/gpu/drm/amd/amdgpu/si.c temp = RREG32(CONFIG_CNTL); RREG32 1219 drivers/gpu/drm/amd/amdgpu/si.c tmp = RREG32(CG_CLKPIN_CNTL_2); RREG32 1223 drivers/gpu/drm/amd/amdgpu/si.c tmp = RREG32(CG_CLKPIN_CNTL); RREG32 1246 drivers/gpu/drm/amd/amdgpu/si.c RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); RREG32 1257 drivers/gpu/drm/amd/amdgpu/si.c RREG32(mmHDP_DEBUG0); RREG32 1421 drivers/gpu/drm/amd/amdgpu/si.c return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) RREG32 1789 drivers/gpu/drm/amd/amdgpu/si.c r = RREG32(EVERGREEN_PIF_PHY0_DATA); RREG32 1811 drivers/gpu/drm/amd/amdgpu/si.c r = RREG32(EVERGREEN_PIF_PHY1_DATA); RREG32 1971 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(THM_CLK_CNTL); RREG32 1977 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(MISC_CLK_CNTL); RREG32 1983 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(CG_CLKPIN_CNTL); RREG32 1988 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(CG_CLKPIN_CNTL_2); RREG32 1993 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(MPLL_BYPASSCLK_SEL); RREG32 1999 drivers/gpu/drm/amd/amdgpu/si.c orig = data = RREG32(SPLL_CNTL_MODE); RREG32 51 drivers/gpu/drm/amd/amdgpu/si_dma.c return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; RREG32 121 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); RREG32 172 drivers/gpu/drm/amd/amdgpu/si_dma.c dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); RREG32 559 drivers/gpu/drm/amd/amdgpu/si_dma.c u32 tmp = RREG32(SRBM_STATUS2); RREG32 597 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); RREG32 602 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); RREG32 613 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); RREG32 618 drivers/gpu/drm/amd/amdgpu/si_dma.c sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); RREG32 659 drivers/gpu/drm/amd/amdgpu/si_dma.c orig = data = RREG32(DMA_POWER_CNTL + offset); RREG32 671 drivers/gpu/drm/amd/amdgpu/si_dma.c orig = data = RREG32(DMA_POWER_CNTL + offset); RREG32 676 drivers/gpu/drm/amd/amdgpu/si_dma.c orig = data = RREG32(DMA_CLK_CTRL + offset); RREG32 2201 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; RREG32 2769 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; RREG32 2854 drivers/gpu/drm/amd/amdgpu/si_dpm.c data = RREG32(config_regs->offset); RREG32 3091 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 3092 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 3093 drivers/gpu/drm/amd/amdgpu/si_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; RREG32 3096 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); RREG32 3097 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); RREG32 3098 drivers/gpu/drm/amd/amdgpu/si_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; RREG32 3101 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); RREG32 3102 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); RREG32 3103 drivers/gpu/drm/amd/amdgpu/si_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; RREG32 3106 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); RREG32 3107 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); RREG32 3108 drivers/gpu/drm/amd/amdgpu/si_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; RREG32 3139 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; RREG32 3396 drivers/gpu/drm/amd/amdgpu/si_dpm.c return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); RREG32 3670 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 3676 drivers/gpu/drm/amd/amdgpu/si_dpm.c width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; RREG32 3678 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 4032 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); RREG32 4033 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 4034 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 4035 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); RREG32 4036 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 4037 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 4038 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); RREG32 4039 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); RREG32 4040 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); RREG32 4041 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); RREG32 4042 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); RREG32 4043 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); RREG32 4044 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); RREG32 4045 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); RREG32 4046 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); RREG32 4082 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (RREG32(SMC_RESP_0) == 1) RREG32 4152 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); RREG32 4165 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); RREG32 4266 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 4744 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; RREG32 4751 drivers/gpu/drm/amd/amdgpu/si_dpm.c dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); RREG32 4772 drivers/gpu/drm/amd/amdgpu/si_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 4773 drivers/gpu/drm/amd/amdgpu/si_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 4774 drivers/gpu/drm/amd/amdgpu/si_dpm.c burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; RREG32 5466 drivers/gpu/drm/amd/amdgpu/si_dpm.c (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && RREG32 5485 drivers/gpu/drm/amd/amdgpu/si_dpm.c ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) RREG32 5486 drivers/gpu/drm/amd/amdgpu/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 5488 drivers/gpu/drm/amd/amdgpu/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; RREG32 5496 drivers/gpu/drm/amd/amdgpu/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 5827 drivers/gpu/drm/amd/amdgpu/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_EMRS); RREG32 5838 drivers/gpu/drm/amd/amdgpu/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS); RREG32 5862 drivers/gpu/drm/amd/amdgpu/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS1); RREG32 5999 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); RREG32 6000 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); RREG32 6001 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); RREG32 6002 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); RREG32 6003 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); RREG32 6004 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); RREG32 6005 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); RREG32 6006 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); RREG32 6007 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); RREG32 6008 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); RREG32 6009 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); RREG32 6010 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); RREG32 6011 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); RREG32 6012 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); RREG32 6398 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 thermal_int = RREG32(CG_THERMAL_INT); RREG32 6449 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; RREG32 6451 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; RREG32 6456 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32 6460 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32 6481 drivers/gpu/drm/amd/amdgpu/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6517 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; RREG32 6573 drivers/gpu/drm/amd/amdgpu/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6574 drivers/gpu/drm/amd/amdgpu/si_dpm.c duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; RREG32 6607 drivers/gpu/drm/amd/amdgpu/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6616 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; RREG32 6650 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; RREG32 6667 drivers/gpu/drm/amd/amdgpu/si_dpm.c tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; RREG32 6696 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; RREG32 6712 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32 6716 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32 6736 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; RREG32 6741 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; RREG32 7491 drivers/gpu/drm/amd/amdgpu/si_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 7857 drivers/gpu/drm/amd/amdgpu/si_dpm.c temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> RREG32 7992 drivers/gpu/drm/amd/amdgpu/si_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 35 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 36 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 47 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 48 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 69 drivers/gpu/drm/amd/amdgpu/si_ih.c interrupt_cntl = RREG32(INTERRUPT_CNTL); RREG32 117 drivers/gpu/drm/amd/amdgpu/si_ih.c tmp = RREG32(IH_RB_CNTL); RREG32 215 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 tmp = RREG32(SRBM_STATUS); RREG32 241 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 tmp = RREG32(SRBM_STATUS); RREG32 247 drivers/gpu/drm/amd/amdgpu/si_ih.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 251 drivers/gpu/drm/amd/amdgpu/si_ih.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 257 drivers/gpu/drm/amd/amdgpu/si_ih.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 86 drivers/gpu/drm/amd/amdgpu/si_smc.c original_data = RREG32(SMC_IND_DATA_0); RREG32 124 drivers/gpu/drm/amd/amdgpu/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 125 drivers/gpu/drm/amd/amdgpu/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 126 drivers/gpu/drm/amd/amdgpu/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 127 drivers/gpu/drm/amd/amdgpu/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 176 drivers/gpu/drm/amd/amdgpu/si_smc.c tmp = RREG32(SMC_RESP_0); RREG32 182 drivers/gpu/drm/amd/amdgpu/si_smc.c return (PPSMC_Result)RREG32(SMC_RESP_0); RREG32 254 drivers/gpu/drm/amd/amdgpu/si_smc.c *value = RREG32(SMC_IND_DATA_0); RREG32 106 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 107 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32(data); RREG32 121 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 123 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(data); RREG32 137 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 138 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32(data); RREG32 142 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 143 drivers/gpu/drm/amd/amdgpu/soc15.c r |= ((u64)RREG32(data) << 32); RREG32 158 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 160 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(data); RREG32 164 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(address); RREG32 166 drivers/gpu/drm/amd/amdgpu/soc15.c (void)RREG32(data); RREG32 180 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32(data); RREG32 208 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32(data); RREG32 344 drivers/gpu/drm/amd/amdgpu/soc15.c dw_ptr[i] = RREG32(rom_data_offset); RREG32 380 drivers/gpu/drm/amd/amdgpu/soc15.c val = RREG32(reg_offset); RREG32 399 drivers/gpu/drm/amd/amdgpu/soc15.c return RREG32(reg_offset); RREG32 451 drivers/gpu/drm/amd/amdgpu/soc15.c tmp = RREG32(reg); RREG32 1351 drivers/gpu/drm/amd/amdgpu/soc15.c def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); RREG32 1367 drivers/gpu/drm/amd/amdgpu/soc15.c def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); RREG32 1383 drivers/gpu/drm/amd/amdgpu/soc15.c def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); RREG32 1412 drivers/gpu/drm/amd/amdgpu/soc15.c def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); RREG32 1428 drivers/gpu/drm/amd/amdgpu/soc15.c def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); RREG32 1504 drivers/gpu/drm/amd/amdgpu/soc15.c data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); RREG32 1509 drivers/gpu/drm/amd/amdgpu/soc15.c data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); RREG32 1514 drivers/gpu/drm/amd/amdgpu/soc15.c data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); RREG32 1519 drivers/gpu/drm/amd/amdgpu/soc15.c data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); RREG32 32 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ RREG32 36 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) RREG32 39 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) RREG32 53 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ RREG32 62 drivers/gpu/drm/amd/amdgpu/soc15_common.h tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ RREG32 86 drivers/gpu/drm/amd/amdgpu/soc15_common.h u32 tmp = RREG32(r1); \ RREG32 124 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ RREG32 62 drivers/gpu/drm/amd/amdgpu/tonga_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 79 drivers/gpu/drm/amd/amdgpu/tonga_ih.c u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); RREG32 113 drivers/gpu/drm/amd/amdgpu/tonga_ih.c interrupt_cntl = RREG32(mmINTERRUPT_CNTL); RREG32 145 drivers/gpu/drm/amd/amdgpu/tonga_ih.c ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); RREG32 207 drivers/gpu/drm/amd/amdgpu/tonga_ih.c tmp = RREG32(mmIH_RB_CNTL); RREG32 345 drivers/gpu/drm/amd/amdgpu/tonga_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 361 drivers/gpu/drm/amd/amdgpu/tonga_ih.c tmp = RREG32(mmSRBM_STATUS); RREG32 373 drivers/gpu/drm/amd/amdgpu/tonga_ih.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 420 drivers/gpu/drm/amd/amdgpu/tonga_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 424 drivers/gpu/drm/amd/amdgpu/tonga_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 430 drivers/gpu/drm/amd/amdgpu/tonga_ih.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 95 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); RREG32 99 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); RREG32 110 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); RREG32 225 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); RREG32 62 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c return RREG32(mmUVD_RBC_RB_RPTR); RREG32 76 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c return RREG32(mmUVD_RBC_RB_WPTR); RREG32 215 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c if (RREG32(mmUVD_STATUS) != 0) RREG32 290 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = RREG32(mmUVD_MPC_CNTL); RREG32 319 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c status = RREG32(mmUVD_STATUS); RREG32 360 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); RREG32 390 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c status = RREG32(mmUVD_STATUS); RREG32 401 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c status = RREG32(mmUVD_LMI_STATUS); RREG32 415 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c status = RREG32(mmUVD_LMI_STATUS); RREG32 491 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = RREG32(mmUVD_CONTEXT_ID); RREG32 586 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 595 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 609 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = RREG32(mmUVD_CGC_CTRL); RREG32 633 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); RREG32 642 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) RREG32 60 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c return RREG32(mmUVD_RBC_RB_RPTR); RREG32 74 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c return RREG32(mmUVD_RBC_RB_WPTR); RREG32 213 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c if (RREG32(mmUVD_STATUS) != 0) RREG32 364 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c status = RREG32(mmUVD_STATUS); RREG32 418 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); RREG32 507 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c tmp = RREG32(mmUVD_CONTEXT_ID); RREG32 556 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); RREG32 565 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) RREG32 606 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data1 = RREG32(mmUVD_SUVD_CGC_GATE); RREG32 607 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data3 = RREG32(mmUVD_CGC_GATE); RREG32 652 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data = RREG32(mmUVD_CGC_CTRL); RREG32 653 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data2 = RREG32(mmUVD_SUVD_CGC_CTRL); RREG32 700 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data = RREG32(mmUVD_CGC_GATE); RREG32 701 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data1 = RREG32(mmUVD_SUVD_CGC_GATE); RREG32 746 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 755 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 823 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c data = RREG32(mmUVD_CGC_CTRL); RREG32 81 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RBC_RB_RPTR); RREG32 96 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RB_RPTR); RREG32 98 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RB_RPTR2); RREG32 111 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RBC_RB_WPTR); RREG32 126 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RB_WPTR); RREG32 128 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return RREG32(mmUVD_RB_WPTR2); RREG32 540 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (RREG32(mmUVD_STATUS) != 0) RREG32 619 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32(mmUVD_CGC_GATE); RREG32 620 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data1 = RREG32(mmUVD_SUVD_CGC_GATE); RREG32 781 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c status = RREG32(mmUVD_STATUS); RREG32 835 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); RREG32 971 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = RREG32(mmUVD_CONTEXT_ID); RREG32 1117 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); RREG32 1137 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1141 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) RREG32 1176 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1180 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1186 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1252 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data1 = RREG32(mmUVD_SUVD_CGC_GATE); RREG32 1253 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data3 = RREG32(mmUVD_CGC_GATE); RREG32 1307 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32(mmUVD_CGC_CTRL); RREG32 1308 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data2 = RREG32(mmUVD_SUVD_CGC_CTRL); RREG32 1356 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32(mmUVD_CGC_GATE); RREG32 1357 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data1 = RREG32(mmUVD_SUVD_CGC_GATE); RREG32 1404 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 1413 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c orig = data = RREG32(mmUVD_CGC_CTRL); RREG32 1486 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c data = RREG32(mmUVD_CGC_CTRL); RREG32 1438 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); RREG32 1458 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c u32 tmp = RREG32(mmSRBM_STATUS); RREG32 1499 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1503 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 1509 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 60 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return RREG32(mmVCE_RB_RPTR); RREG32 62 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return RREG32(mmVCE_RB_RPTR2); RREG32 77 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return RREG32(mmVCE_RB_WPTR); RREG32 79 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return RREG32(mmVCE_RB_WPTR2); RREG32 105 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t status = RREG32(mmVCE_LMI_STATUS); RREG32 122 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c uint32_t status = RREG32(mmVCE_STATUS); RREG32 151 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_CLOCK_GATING_A); RREG32 157 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 162 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_CLOCK_GATING_B); RREG32 208 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); RREG32 294 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c status = RREG32(mmVCE_LMI_STATUS); RREG32 315 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_CLOCK_GATING_B); RREG32 319 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 323 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); RREG32 329 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_CLOCK_GATING_B); RREG32 334 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 339 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); RREG32 352 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c tmp = RREG32(mmVCE_CLOCK_GATING_B); RREG32 365 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 371 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); RREG32 90 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_RPTR); RREG32 92 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_RPTR2); RREG32 94 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_RPTR3); RREG32 122 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_WPTR); RREG32 124 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_WPTR2); RREG32 126 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c v = RREG32(mmVCE_RB_WPTR3); RREG32 182 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_CLOCK_GATING_B); RREG32 187 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 192 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_CLOCK_GATING_2); RREG32 197 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); RREG32 201 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); RREG32 208 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_CLOCK_GATING_B); RREG32 213 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 217 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_CLOCK_GATING_2); RREG32 221 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); RREG32 225 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); RREG32 241 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t status = RREG32(mmVCE_STATUS); RREG32 583 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c return !(RREG32(mmSRBM_STATUS2) & mask); RREG32 624 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { RREG32 629 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { RREG32 657 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 661 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 667 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 758 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c uint32_t data = RREG32(mmVCE_CLOCK_GATING_A); RREG32 764 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_UENC_CLOCK_GATING); RREG32 826 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c data = RREG32(mmVCE_CLOCK_GATING_A); RREG32 66 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); RREG32 68 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); RREG32 70 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); RREG32 88 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); RREG32 90 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); RREG32 92 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); RREG32 131 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); RREG32 167 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID)); RREG32 186 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); RREG32 190 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); RREG32 675 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return !(RREG32(mmSRBM_STATUS2) & mask); RREG32 716 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { RREG32 721 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { RREG32 749 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 753 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 759 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c tmp = RREG32(mmSRBM_SOFT_RESET); RREG32 797 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL)); RREG32 821 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); RREG32 826 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); RREG32 831 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); RREG32 836 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); RREG32 840 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); RREG32 847 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); RREG32 852 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); RREG32 856 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); RREG32 860 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); RREG32 864 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); RREG32 911 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A); RREG32 917 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING); RREG32 686 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; RREG32 762 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)); RREG32 2112 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); RREG32 143 drivers/gpu/drm/amd/amdgpu/vi.c r = RREG32(mmMP0PUB_IND_DATA); RREG32 165 drivers/gpu/drm/amd/amdgpu/vi.c r = RREG32(mmUVD_CTX_DATA); RREG32 187 drivers/gpu/drm/amd/amdgpu/vi.c r = RREG32(mmDIDT_IND_DATA); RREG32 209 drivers/gpu/drm/amd/amdgpu/vi.c r = RREG32(mmGC_CAC_IND_DATA); RREG32 384 drivers/gpu/drm/amd/amdgpu/vi.c bus_cntl = RREG32(mmBUS_CNTL); RREG32 386 drivers/gpu/drm/amd/amdgpu/vi.c d1vga_control = RREG32(mmD1VGA_CONTROL); RREG32 387 drivers/gpu/drm/amd/amdgpu/vi.c d2vga_control = RREG32(mmD2VGA_CONTROL); RREG32 388 drivers/gpu/drm/amd/amdgpu/vi.c vga_render_control = RREG32(mmVGA_RENDER_CONTROL); RREG32 445 drivers/gpu/drm/amd/amdgpu/vi.c dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); RREG32 457 drivers/gpu/drm/amd/amdgpu/vi.c reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); RREG32 575 drivers/gpu/drm/amd/amdgpu/vi.c val = RREG32(reg_offset); RREG32 642 drivers/gpu/drm/amd/amdgpu/vi.c return RREG32(reg_offset); RREG32 681 drivers/gpu/drm/amd/amdgpu/vi.c if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { RREG32 722 drivers/gpu/drm/amd/amdgpu/vi.c return RREG32(mmCONFIG_MEMSIZE); RREG32 886 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32(mmBIF_DOORBELL_APER_EN); RREG32 905 drivers/gpu/drm/amd/amdgpu/vi.c return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) RREG32 913 drivers/gpu/drm/amd/amdgpu/vi.c RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); RREG32 924 drivers/gpu/drm/amd/amdgpu/vi.c RREG32(mmHDP_DEBUG0); RREG32 1382 drivers/gpu/drm/amd/amdgpu/vi.c temp = data = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 1398 drivers/gpu/drm/amd/amdgpu/vi.c temp = data = RREG32(mmHDP_MEM_POWER_LS); RREG32 1414 drivers/gpu/drm/amd/amdgpu/vi.c temp = data = RREG32(0x157a); RREG32 1630 drivers/gpu/drm/amd/amdgpu/vi.c data = RREG32(mmHDP_MEM_POWER_LS); RREG32 1635 drivers/gpu/drm/amd/amdgpu/vi.c data = RREG32(mmHDP_HOST_PATH_CNTL); RREG32 34 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c data = RREG32(reg); RREG32 56 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c data = RREG32(reg); RREG32 41 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c data = RREG32(0x12075); RREG32 49 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) { RREG32 122 drivers/gpu/drm/mgag200/mgag200_main.c mdev->unique_rev_id = RREG32(0x1e24); RREG32 82 drivers/gpu/drm/mgag200/mgag200_mode.c status = RREG32(MGAREG_Status); RREG32 87 drivers/gpu/drm/mgag200/mgag200_mode.c status = RREG32(MGAREG_Status); RREG32 1144 drivers/gpu/drm/mgag200/mgag200_mode.c u32 mem_ctl = RREG32(MGAREG_MEMCTL); RREG32 238 drivers/gpu/drm/radeon/atombios_crtc.c vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); RREG32 403 drivers/gpu/drm/radeon/atombios_crtc.c ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); RREG32 408 drivers/gpu/drm/radeon/atombios_crtc.c ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); RREG32 419 drivers/gpu/drm/radeon/atombios_crtc.c ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); RREG32 424 drivers/gpu/drm/radeon/atombios_crtc.c ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); RREG32 1714 drivers/gpu/drm/radeon/atombios_crtc.c disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); RREG32 1719 drivers/gpu/drm/radeon/atombios_crtc.c disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); RREG32 1722 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); RREG32 1723 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); RREG32 49 drivers/gpu/drm/radeon/atombios_encoders.c bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); RREG32 51 drivers/gpu/drm/radeon/atombios_encoders.c bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); RREG32 66 drivers/gpu/drm/radeon/atombios_encoders.c bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); RREG32 68 drivers/gpu/drm/radeon/atombios_encoders.c bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); RREG32 1559 drivers/gpu/drm/radeon/atombios_encoders.c temp = RREG32(reg); RREG32 1634 drivers/gpu/drm/radeon/atombios_encoders.c u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); RREG32 2073 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); RREG32 2402 drivers/gpu/drm/radeon/atombios_encoders.c bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); RREG32 2404 drivers/gpu/drm/radeon/atombios_encoders.c bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); RREG32 2451 drivers/gpu/drm/radeon/atombios_encoders.c bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); RREG32 1345 drivers/gpu/drm/radeon/btc_dpm.c bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; RREG32 1364 drivers/gpu/drm/radeon/btc_dpm.c bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; RREG32 1448 drivers/gpu/drm/radeon/btc_dpm.c tmp = RREG32(sequence[i]); RREG32 1745 drivers/gpu/drm/radeon/btc_dpm.c if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1) RREG32 1760 drivers/gpu/drm/radeon/btc_dpm.c arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 1761 drivers/gpu/drm/radeon/btc_dpm.c arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 1762 drivers/gpu/drm/radeon/btc_dpm.c arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE); RREG32 1763 drivers/gpu/drm/radeon/btc_dpm.c arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); RREG32 1927 drivers/gpu/drm/radeon/btc_dpm.c tmp = RREG32(MC_PMG_CMD_EMRS); RREG32 1940 drivers/gpu/drm/radeon/btc_dpm.c tmp = RREG32(MC_PMG_CMD_MRS); RREG32 1956 drivers/gpu/drm/radeon/btc_dpm.c tmp = RREG32(MC_PMG_CMD_MRS1); RREG32 2031 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); RREG32 2032 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); RREG32 2033 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); RREG32 2034 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); RREG32 2035 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); RREG32 2036 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); RREG32 2037 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); RREG32 2038 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); RREG32 2039 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); RREG32 2040 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); RREG32 2041 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); RREG32 2074 drivers/gpu/drm/radeon/btc_dpm.c tmp = RREG32(MC_PMG_AUTO_CFG); RREG32 2744 drivers/gpu/drm/radeon/btc_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2769 drivers/gpu/drm/radeon/btc_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2792 drivers/gpu/drm/radeon/btc_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 590 drivers/gpu/drm/radeon/ci_dpm.c data = RREG32(config_regs->offset << 2); RREG32 1668 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(SMC_RESP_0); RREG32 1673 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(SMC_RESP_0); RREG32 1693 drivers/gpu/drm/radeon/ci_dpm.c *parameter = RREG32(SMC_MSG_ARG_0); RREG32 1886 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); RREG32 1887 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); RREG32 1888 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); RREG32 1889 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); RREG32 1890 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); RREG32 1891 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); RREG32 1892 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); RREG32 1893 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); RREG32 1894 drivers/gpu/drm/radeon/ci_dpm.c pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); RREG32 1945 drivers/gpu/drm/radeon/ci_dpm.c if (RREG32(SMC_RESP_0) == 1) RREG32 2503 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 2533 drivers/gpu/drm/radeon/ci_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 2534 drivers/gpu/drm/radeon/ci_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 2535 drivers/gpu/drm/radeon/ci_dpm.c burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; RREG32 2932 drivers/gpu/drm/radeon/ci_dpm.c (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && RREG32 2953 drivers/gpu/drm/radeon/ci_dpm.c ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) RREG32 2954 drivers/gpu/drm/radeon/ci_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 2956 drivers/gpu/drm/radeon/ci_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; RREG32 2962 drivers/gpu/drm/radeon/ci_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 4348 drivers/gpu/drm/radeon/ci_dpm.c temp_reg = RREG32(MC_PMG_CMD_EMRS); RREG32 4359 drivers/gpu/drm/radeon/ci_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS); RREG32 4385 drivers/gpu/drm/radeon/ci_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS1); RREG32 4541 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 4615 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(MC_SEQ_IO_DEBUG_DATA); RREG32 4636 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); RREG32 4637 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); RREG32 4638 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); RREG32 4639 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); RREG32 4640 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); RREG32 4641 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); RREG32 4642 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); RREG32 4643 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); RREG32 4644 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); RREG32 4645 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); RREG32 4646 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); RREG32 4647 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); RREG32 4648 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); RREG32 4649 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); RREG32 4650 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); RREG32 4651 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); RREG32 4652 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); RREG32 4653 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); RREG32 4654 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); RREG32 4655 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); RREG32 5098 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 88 drivers/gpu/drm/radeon/ci_smc.c original_data = RREG32(SMC_IND_DATA_0); RREG32 255 drivers/gpu/drm/radeon/ci_smc.c *value = RREG32(SMC_IND_DATA_0); RREG32 178 drivers/gpu/drm/radeon/cik.c *val = RREG32(reg); RREG32 195 drivers/gpu/drm/radeon/cik.c r = RREG32(CIK_DIDT_IND_DATA); RREG32 257 drivers/gpu/drm/radeon/cik.c (void)RREG32(PCIE_INDEX); RREG32 258 drivers/gpu/drm/radeon/cik.c r = RREG32(PCIE_DATA); RREG32 269 drivers/gpu/drm/radeon/cik.c (void)RREG32(PCIE_INDEX); RREG32 271 drivers/gpu/drm/radeon/cik.c (void)RREG32(PCIE_DATA); RREG32 1915 drivers/gpu/drm/radeon/cik.c running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; RREG32 1933 drivers/gpu/drm/radeon/cik.c tmp = RREG32(MC_SEQ_MISC0); RREG32 1956 drivers/gpu/drm/radeon/cik.c if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) RREG32 1961 drivers/gpu/drm/radeon/cik.c if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) RREG32 3091 drivers/gpu/drm/radeon/cik.c data = RREG32(CC_RB_BACKEND_DISABLE); RREG32 3096 drivers/gpu/drm/radeon/cik.c data |= RREG32(GC_USER_RB_BACKEND_DISABLE); RREG32 3184 drivers/gpu/drm/radeon/cik.c u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); RREG32 3278 drivers/gpu/drm/radeon/cik.c mc_shared_chmap = RREG32(MC_SHARED_CHMAP); RREG32 3279 drivers/gpu/drm/radeon/cik.c mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); RREG32 3368 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SPI_CONFIG_CNTL); RREG32 3376 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DB_DEBUG2) & ~0xf00fffff; RREG32 3380 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DB_DEBUG3) & ~0x0002021c; RREG32 3384 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CB_HW_CONTROL) & ~0x00010000; RREG32 3410 drivers/gpu/drm/radeon/cik.c tmp = RREG32(HDP_MISC_CNTL); RREG32 3414 drivers/gpu/drm/radeon/cik.c hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); RREG32 3484 drivers/gpu/drm/radeon/cik.c tmp = RREG32(scratch); RREG32 3829 drivers/gpu/drm/radeon/cik.c tmp = RREG32(scratch); RREG32 4135 drivers/gpu/drm/radeon/cik.c rptr = RREG32(CP_RB0_RPTR); RREG32 4143 drivers/gpu/drm/radeon/cik.c return RREG32(CP_RB0_WPTR); RREG32 4150 drivers/gpu/drm/radeon/cik.c (void)RREG32(CP_RB0_WPTR); RREG32 4163 drivers/gpu/drm/radeon/cik.c rptr = RREG32(CP_HQD_PQ_RPTR); RREG32 4182 drivers/gpu/drm/radeon/cik.c wptr = RREG32(CP_HQD_PQ_WPTR); RREG32 4205 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); RREG32 4209 drivers/gpu/drm/radeon/cik.c if (RREG32(CP_HQD_ACTIVE) & 1) { RREG32 4212 drivers/gpu/drm/radeon/cik.c if (!(RREG32(CP_HQD_ACTIVE) & 1)) RREG32 4539 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CP_CPF_DEBUG); RREG32 4561 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CP_HPD_EOP_CONTROL); RREG32 4624 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); RREG32 4630 drivers/gpu/drm/radeon/cik.c RREG32(CP_HQD_PQ_DOORBELL_CONTROL); RREG32 4642 drivers/gpu/drm/radeon/cik.c if (RREG32(CP_HQD_ACTIVE) & 1) { RREG32 4645 drivers/gpu/drm/radeon/cik.c if (!(RREG32(CP_HQD_ACTIVE) & 1)) RREG32 4660 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); RREG32 4672 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); RREG32 4716 drivers/gpu/drm/radeon/cik.c RREG32(CP_HQD_PQ_DOORBELL_CONTROL); RREG32 4734 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR); RREG32 4810 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS)); RREG32 4812 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS2)); RREG32 4814 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS_SE0)); RREG32 4816 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS_SE1)); RREG32 4818 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS_SE2)); RREG32 4820 drivers/gpu/drm/radeon/cik.c RREG32(GRBM_STATUS_SE3)); RREG32 4822 drivers/gpu/drm/radeon/cik.c RREG32(SRBM_STATUS)); RREG32 4824 drivers/gpu/drm/radeon/cik.c RREG32(SRBM_STATUS2)); RREG32 4826 drivers/gpu/drm/radeon/cik.c RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); RREG32 4828 drivers/gpu/drm/radeon/cik.c RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); RREG32 4829 drivers/gpu/drm/radeon/cik.c dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT)); RREG32 4831 drivers/gpu/drm/radeon/cik.c RREG32(CP_STALLED_STAT1)); RREG32 4833 drivers/gpu/drm/radeon/cik.c RREG32(CP_STALLED_STAT2)); RREG32 4835 drivers/gpu/drm/radeon/cik.c RREG32(CP_STALLED_STAT3)); RREG32 4837 drivers/gpu/drm/radeon/cik.c RREG32(CP_CPF_BUSY_STAT)); RREG32 4839 drivers/gpu/drm/radeon/cik.c RREG32(CP_CPF_STALLED_STAT1)); RREG32 4840 drivers/gpu/drm/radeon/cik.c dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS)); RREG32 4841 drivers/gpu/drm/radeon/cik.c dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT)); RREG32 4843 drivers/gpu/drm/radeon/cik.c RREG32(CP_CPC_STALLED_STAT1)); RREG32 4844 drivers/gpu/drm/radeon/cik.c dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS)); RREG32 4862 drivers/gpu/drm/radeon/cik.c tmp = RREG32(GRBM_STATUS); RREG32 4875 drivers/gpu/drm/radeon/cik.c tmp = RREG32(GRBM_STATUS2); RREG32 4880 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); RREG32 4885 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); RREG32 4890 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SRBM_STATUS2); RREG32 4898 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SRBM_STATUS); RREG32 4949 drivers/gpu/drm/radeon/cik.c RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); RREG32 4951 drivers/gpu/drm/radeon/cik.c RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); RREG32 4968 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); RREG32 4974 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); RREG32 5023 drivers/gpu/drm/radeon/cik.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 5027 drivers/gpu/drm/radeon/cik.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 5033 drivers/gpu/drm/radeon/cik.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 5037 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 5041 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 5047 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 5068 drivers/gpu/drm/radeon/cik.c save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE); RREG32 5069 drivers/gpu/drm/radeon/cik.c save->gmcon_misc = RREG32(GMCON_MISC); RREG32 5070 drivers/gpu/drm/radeon/cik.c save->gmcon_misc3 = RREG32(GMCON_MISC3); RREG32 5171 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); RREG32 5175 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); RREG32 5203 drivers/gpu/drm/radeon/cik.c if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) RREG32 5349 drivers/gpu/drm/radeon/cik.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 5355 drivers/gpu/drm/radeon/cik.c tmp = RREG32(MC_SHARED_CHMAP); RREG32 5391 drivers/gpu/drm/radeon/cik.c rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 5392 drivers/gpu/drm/radeon/cik.c rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 5510 drivers/gpu/drm/radeon/cik.c u32 tmp = RREG32(CHUB_CONTROL); RREG32 5560 drivers/gpu/drm/radeon/cik.c rdev->vm_manager.saved_table_addr[i] = RREG32(reg); RREG32 5635 drivers/gpu/drm/radeon/cik.c u64 tmp = RREG32(MC_VM_FB_OFFSET); RREG32 5775 drivers/gpu/drm/radeon/cik.c u32 tmp = RREG32(CP_INT_CNTL_RING0); RREG32 5788 drivers/gpu/drm/radeon/cik.c tmp = RREG32(RLC_LB_CNTL); RREG32 5805 drivers/gpu/drm/radeon/cik.c if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0) RREG32 5815 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) RREG32 5825 drivers/gpu/drm/radeon/cik.c tmp = RREG32(RLC_CNTL); RREG32 5834 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_CNTL); RREG32 5843 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0) RREG32 5863 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_GPM_STAT) & mask) == mask) RREG32 5869 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_GPR_REG2) & REQ) == 0) RREG32 5934 drivers/gpu/drm/radeon/cik.c tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc; RREG32 6009 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_CGCG_CGLS_CTRL); RREG32 6028 drivers/gpu/drm/radeon/cik.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 6029 drivers/gpu/drm/radeon/cik.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 6030 drivers/gpu/drm/radeon/cik.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 6031 drivers/gpu/drm/radeon/cik.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 6048 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(CP_MEM_SLP_CNTL); RREG32 6055 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); RREG32 6072 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(CGTS_SM_CTRL_REG); RREG32 6087 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); RREG32 6092 drivers/gpu/drm/radeon/cik.c data = RREG32(RLC_MEM_SLP_CNTL); RREG32 6098 drivers/gpu/drm/radeon/cik.c data = RREG32(CP_MEM_SLP_CNTL); RREG32 6104 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(CGTS_SM_CTRL_REG); RREG32 6141 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(mc_cg_registers[i]); RREG32 6158 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(mc_cg_registers[i]); RREG32 6177 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); RREG32 6182 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); RREG32 6195 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); RREG32 6200 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); RREG32 6205 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); RREG32 6210 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); RREG32 6227 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(UVD_CGC_CTRL); RREG32 6236 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(UVD_CGC_CTRL); RREG32 6266 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(HDP_HOST_PATH_CNTL); RREG32 6282 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(HDP_MEM_POWER_LS); RREG32 6372 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6386 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6399 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6412 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6515 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6520 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_AUTO_PG_CTRL); RREG32 6525 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6530 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_AUTO_PG_CTRL); RREG32 6535 drivers/gpu/drm/radeon/cik.c data = RREG32(DB_RENDER_CONTROL); RREG32 6545 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); RREG32 6546 drivers/gpu/drm/radeon/cik.c tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); RREG32 6589 drivers/gpu/drm/radeon/cik.c tmp = RREG32(RLC_MAX_PG_CU); RREG32 6600 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6614 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6647 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_PG_CNTL); RREG32 6655 drivers/gpu/drm/radeon/cik.c data = RREG32(CP_RB_WPTR_POLL_CNTL); RREG32 6663 drivers/gpu/drm/radeon/cik.c data = RREG32(RLC_PG_DELAY_2); RREG32 6668 drivers/gpu/drm/radeon/cik.c data = RREG32(RLC_AUTO_PG_CTRL); RREG32 6829 drivers/gpu/drm/radeon/cik.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 6830 drivers/gpu/drm/radeon/cik.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 6848 drivers/gpu/drm/radeon/cik.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 6849 drivers/gpu/drm/radeon/cik.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 6874 drivers/gpu/drm/radeon/cik.c tmp = RREG32(CP_INT_CNTL_RING0) & RREG32 6878 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 6880 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 6924 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6926 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6928 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6930 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6932 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6934 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 6974 drivers/gpu/drm/radeon/cik.c interrupt_cntl = RREG32(INTERRUPT_CNTL); RREG32 7052 drivers/gpu/drm/radeon/cik.c cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & RREG32 7056 drivers/gpu/drm/radeon/cik.c hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7057 drivers/gpu/drm/radeon/cik.c hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7058 drivers/gpu/drm/radeon/cik.c hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7059 drivers/gpu/drm/radeon/cik.c hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7060 drivers/gpu/drm/radeon/cik.c hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7061 drivers/gpu/drm/radeon/cik.c hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); RREG32 7063 drivers/gpu/drm/radeon/cik.c dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 7064 drivers/gpu/drm/radeon/cik.c dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 7066 drivers/gpu/drm/radeon/cik.c cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7067 drivers/gpu/drm/radeon/cik.c cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7068 drivers/gpu/drm/radeon/cik.c cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7069 drivers/gpu/drm/radeon/cik.c cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7070 drivers/gpu/drm/radeon/cik.c cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7071 drivers/gpu/drm/radeon/cik.c cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7072 drivers/gpu/drm/radeon/cik.c cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7073 drivers/gpu/drm/radeon/cik.c cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; RREG32 7286 drivers/gpu/drm/radeon/cik.c RREG32(SRBM_STATUS); RREG32 7304 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); RREG32 7305 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); RREG32 7306 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); RREG32 7307 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); RREG32 7308 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); RREG32 7309 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); RREG32 7310 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); RREG32 7312 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + RREG32 7314 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + RREG32 7317 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + RREG32 7319 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + RREG32 7323 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + RREG32 7325 drivers/gpu/drm/radeon/cik.c rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + RREG32 7379 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD1_INT_CONTROL); RREG32 7384 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD2_INT_CONTROL); RREG32 7389 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD3_INT_CONTROL); RREG32 7394 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD4_INT_CONTROL); RREG32 7399 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD5_INT_CONTROL); RREG32 7404 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD6_INT_CONTROL); RREG32 7409 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD1_INT_CONTROL); RREG32 7414 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD2_INT_CONTROL); RREG32 7419 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD3_INT_CONTROL); RREG32 7424 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD4_INT_CONTROL); RREG32 7429 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD5_INT_CONTROL); RREG32 7434 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DC_HPD6_INT_CONTROL); RREG32 7503 drivers/gpu/drm/radeon/cik.c wptr = RREG32(IH_RB_WPTR); RREG32 7514 drivers/gpu/drm/radeon/cik.c tmp = RREG32(IH_RB_CNTL); RREG32 7902 drivers/gpu/drm/radeon/cik.c DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); RREG32 7911 drivers/gpu/drm/radeon/cik.c addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 7912 drivers/gpu/drm/radeon/cik.c status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 7913 drivers/gpu/drm/radeon/cik.c mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); RREG32 8861 drivers/gpu/drm/radeon/cik.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & RREG32 8894 drivers/gpu/drm/radeon/cik.c u32 tmp = RREG32(MC_SHARED_CHMAP); RREG32 9353 drivers/gpu/drm/radeon/cik.c wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); RREG32 9362 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); RREG32 9422 drivers/gpu/drm/radeon/cik.c clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | RREG32 9423 drivers/gpu/drm/radeon/cik.c ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 76 drivers/gpu/drm/radeon/cik_sdma.c rptr = RREG32(reg); RREG32 100 drivers/gpu/drm/radeon/cik_sdma.c return (RREG32(reg) & 0x3fffc) >> 2; RREG32 122 drivers/gpu/drm/radeon/cik_sdma.c (void)RREG32(reg); RREG32 264 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); RREG32 278 drivers/gpu/drm/radeon/cik_sdma.c (void)RREG32(SRBM_SOFT_RESET); RREG32 281 drivers/gpu/drm/radeon/cik_sdma.c (void)RREG32(SRBM_SOFT_RESET); RREG32 314 drivers/gpu/drm/radeon/cik_sdma.c value = RREG32(SDMA0_CNTL + reg_offset); RREG32 346 drivers/gpu/drm/radeon/cik_sdma.c me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); RREG32 61 drivers/gpu/drm/radeon/cypress_dpm.c bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; RREG32 108 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 149 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 507 drivers/gpu/drm/radeon/cypress_dpm.c mc_seq_misc7 = RREG32(MC_SEQ_MISC7); RREG32 718 drivers/gpu/drm/radeon/cypress_dpm.c ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) RREG32 719 drivers/gpu/drm/radeon/cypress_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 721 drivers/gpu/drm/radeon/cypress_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; RREG32 929 drivers/gpu/drm/radeon/cypress_dpm.c u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME); RREG32 1039 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); RREG32 1110 drivers/gpu/drm/radeon/cypress_dpm.c if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value) RREG32 1125 drivers/gpu/drm/radeon/cypress_dpm.c if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE) RREG32 1154 drivers/gpu/drm/radeon/cypress_dpm.c if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE) RREG32 1173 drivers/gpu/drm/radeon/cypress_dpm.c value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); RREG32 1212 drivers/gpu/drm/radeon/cypress_dpm.c if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)) RREG32 1577 drivers/gpu/drm/radeon/cypress_dpm.c u32 tmp = RREG32(GENERAL_PWRMGT); RREG32 1731 drivers/gpu/drm/radeon/cypress_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 1748 drivers/gpu/drm/radeon/cypress_dpm.c tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); RREG32 1761 drivers/gpu/drm/radeon/cypress_dpm.c tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); RREG32 154 drivers/gpu/drm/radeon/dce3_1_afmt.c dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; RREG32 161 drivers/gpu/drm/radeon/dce3_1_afmt.c dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; RREG32 40 drivers/gpu/drm/radeon/dce6_afmt.c r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); RREG32 304 drivers/gpu/drm/radeon/dce6_afmt.c unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & RREG32 56 drivers/gpu/drm/radeon/evergreen.c r = RREG32(EVERGREEN_CG_IND_DATA); RREG32 78 drivers/gpu/drm/radeon/evergreen.c r = RREG32(EVERGREEN_PIF_PHY0_DATA); RREG32 100 drivers/gpu/drm/radeon/evergreen.c r = RREG32(EVERGREEN_PIF_PHY1_DATA); RREG32 1107 drivers/gpu/drm/radeon/evergreen.c *val = RREG32(reg); RREG32 1159 drivers/gpu/drm/radeon/evergreen.c if (RREG32(status_reg) & DCLK_STATUS) RREG32 1172 drivers/gpu/drm/radeon/evergreen.c u32 cg_scratch = RREG32(CG_SCRATCH1); RREG32 1353 drivers/gpu/drm/radeon/evergreen.c if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) RREG32 1363 drivers/gpu/drm/radeon/evergreen.c pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 1364 drivers/gpu/drm/radeon/evergreen.c pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 1387 drivers/gpu/drm/radeon/evergreen.c if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) RREG32 1431 drivers/gpu/drm/radeon/evergreen.c RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); RREG32 1447 drivers/gpu/drm/radeon/evergreen.c return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & RREG32 1458 drivers/gpu/drm/radeon/evergreen.c toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> RREG32 1460 drivers/gpu/drm/radeon/evergreen.c temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> RREG32 1471 drivers/gpu/drm/radeon/evergreen.c temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> RREG32 1492 drivers/gpu/drm/radeon/evergreen.c u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; RREG32 1682 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); RREG32 1707 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); RREG32 1728 drivers/gpu/drm/radeon/evergreen.c return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE); RREG32 1873 drivers/gpu/drm/radeon/evergreen.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & RREG32 1916 drivers/gpu/drm/radeon/evergreen.c u32 tmp = RREG32(MC_SHARED_CHMAP); RREG32 2284 drivers/gpu/drm/radeon/evergreen.c arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); RREG32 2293 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); RREG32 2363 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_STATUS) & 0x1F00; RREG32 2384 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); RREG32 2580 drivers/gpu/drm/radeon/evergreen.c dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); RREG32 2594 drivers/gpu/drm/radeon/evergreen.c dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]); RREG32 2601 drivers/gpu/drm/radeon/evergreen.c dig_en_be = RREG32(NI_DIG_BE_EN_CNTL + RREG32 2603 drivers/gpu/drm/radeon/evergreen.c uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 + RREG32 2636 drivers/gpu/drm/radeon/evergreen.c stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + RREG32 2647 drivers/gpu/drm/radeon/evergreen.c stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + RREG32 2652 drivers/gpu/drm/radeon/evergreen.c stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + RREG32 2658 drivers/gpu/drm/radeon/evergreen.c fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); RREG32 2671 drivers/gpu/drm/radeon/evergreen.c save->vga_render_control = RREG32(VGA_RENDER_CONTROL); RREG32 2672 drivers/gpu/drm/radeon/evergreen.c save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); RREG32 2679 drivers/gpu/drm/radeon/evergreen.c crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; RREG32 2683 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); RREG32 2692 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); RREG32 2721 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); RREG32 2734 drivers/gpu/drm/radeon/evergreen.c blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); RREG32 2748 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); RREG32 2753 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); RREG32 2787 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); RREG32 2792 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); RREG32 2797 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); RREG32 2803 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); RREG32 2812 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); RREG32 2821 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); RREG32 2827 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); RREG32 2898 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; RREG32 3077 drivers/gpu/drm/radeon/evergreen.c RREG32(GRBM_SOFT_RESET); RREG32 3080 drivers/gpu/drm/radeon/evergreen.c RREG32(GRBM_SOFT_RESET); RREG32 3400 drivers/gpu/drm/radeon/evergreen.c mc_shared_chmap = RREG32(MC_SHARED_CHMAP); RREG32 3404 drivers/gpu/drm/radeon/evergreen.c mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); RREG32 3406 drivers/gpu/drm/radeon/evergreen.c mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); RREG32 3467 drivers/gpu/drm/radeon/evergreen.c rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; RREG32 3488 drivers/gpu/drm/radeon/evergreen.c simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; RREG32 3539 drivers/gpu/drm/radeon/evergreen.c sx_debug_1 = RREG32(SX_DEBUG_1); RREG32 3544 drivers/gpu/drm/radeon/evergreen.c smx_dc_ctl0 = RREG32(SMX_DC_CTL0); RREG32 3570 drivers/gpu/drm/radeon/evergreen.c sq_config = RREG32(SQ_CONFIG); RREG32 3595 drivers/gpu/drm/radeon/evergreen.c sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); RREG32 3697 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(HDP_MISC_CNTL); RREG32 3701 drivers/gpu/drm/radeon/evergreen.c hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); RREG32 3720 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(FUS_MC_ARB_RAMCFG); RREG32 3722 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 3730 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(MC_SHARED_CHMAP); RREG32 3755 drivers/gpu/drm/radeon/evergreen.c rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 3756 drivers/gpu/drm/radeon/evergreen.c rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 3759 drivers/gpu/drm/radeon/evergreen.c rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 3760 drivers/gpu/drm/radeon/evergreen.c rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; RREG32 3772 drivers/gpu/drm/radeon/evergreen.c RREG32(GRBM_STATUS)); RREG32 3774 drivers/gpu/drm/radeon/evergreen.c RREG32(GRBM_STATUS_SE0)); RREG32 3776 drivers/gpu/drm/radeon/evergreen.c RREG32(GRBM_STATUS_SE1)); RREG32 3778 drivers/gpu/drm/radeon/evergreen.c RREG32(SRBM_STATUS)); RREG32 3780 drivers/gpu/drm/radeon/evergreen.c RREG32(SRBM_STATUS2)); RREG32 3782 drivers/gpu/drm/radeon/evergreen.c RREG32(CP_STALLED_STAT1)); RREG32 3784 drivers/gpu/drm/radeon/evergreen.c RREG32(CP_STALLED_STAT2)); RREG32 3786 drivers/gpu/drm/radeon/evergreen.c RREG32(CP_BUSY_STAT)); RREG32 3788 drivers/gpu/drm/radeon/evergreen.c RREG32(CP_STAT)); RREG32 3790 drivers/gpu/drm/radeon/evergreen.c RREG32(DMA_STATUS_REG)); RREG32 3793 drivers/gpu/drm/radeon/evergreen.c RREG32(DMA_STATUS_REG + 0x800)); RREG32 3804 drivers/gpu/drm/radeon/evergreen.c if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { RREG32 3805 drivers/gpu/drm/radeon/evergreen.c crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 3813 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 3832 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(GRBM_STATUS); RREG32 3848 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(DMA_STATUS_REG); RREG32 3853 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_STATUS2); RREG32 3858 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_STATUS); RREG32 3882 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(VM_L2_STATUS); RREG32 3913 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(DMA_RB_CNTL); RREG32 3973 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3977 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3983 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3987 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 3991 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 3997 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 4022 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(DMA_RB_CNTL); RREG32 4045 drivers/gpu/drm/radeon/evergreen.c if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) RREG32 4398 drivers/gpu/drm/radeon/evergreen.c u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; RREG32 4455 drivers/gpu/drm/radeon/evergreen.c return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); RREG32 4468 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; RREG32 4472 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; RREG32 4513 drivers/gpu/drm/radeon/evergreen.c thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & RREG32 4516 drivers/gpu/drm/radeon/evergreen.c thermal_int = RREG32(CG_THERMAL_INT) & RREG32 4519 drivers/gpu/drm/radeon/evergreen.c dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; RREG32 4549 drivers/gpu/drm/radeon/evergreen.c dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; RREG32 4606 drivers/gpu/drm/radeon/evergreen.c RREG32(SRBM_STATUS); RREG32 4620 drivers/gpu/drm/radeon/evergreen.c disp_int[i] = RREG32(evergreen_disp_int_status[i]); RREG32 4621 drivers/gpu/drm/radeon/evergreen.c afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]); RREG32 4623 drivers/gpu/drm/radeon/evergreen.c grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); RREG32 4683 drivers/gpu/drm/radeon/evergreen.c wptr = RREG32(IH_RB_WPTR); RREG32 4694 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(IH_RB_CNTL); RREG32 4835 drivers/gpu/drm/radeon/evergreen.c DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); RREG32 4844 drivers/gpu/drm/radeon/evergreen.c addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 4845 drivers/gpu/drm/radeon/evergreen.c status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 41 drivers/gpu/drm/radeon/evergreen_hdmi.c u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); RREG32 249 drivers/gpu/drm/radeon/evergreen_hdmi.c value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; RREG32 275 drivers/gpu/drm/radeon/evergreen_hdmi.c value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; RREG32 293 drivers/gpu/drm/radeon/evergreen_hdmi.c unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & RREG32 324 drivers/gpu/drm/radeon/evergreen_hdmi.c val = RREG32(HDMI_CONTROL + offset); RREG32 466 drivers/gpu/drm/radeon/evergreen_hdmi.c val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); RREG32 306 drivers/gpu/drm/radeon/kv_dpm.c data = RREG32(config_regs->offset << 2); RREG32 37 drivers/gpu/drm/radeon/kv_smc.c if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0) RREG32 41 drivers/gpu/drm/radeon/kv_smc.c tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK; RREG32 97 drivers/gpu/drm/radeon/kv_smc.c *value = RREG32(SMC_IND_DATA_0); RREG32 138 drivers/gpu/drm/radeon/kv_smc.c original_data = RREG32(SMC_IND_DATA_0); RREG32 192 drivers/gpu/drm/radeon/kv_smc.c original_data= RREG32(SMC_IND_DATA_0); RREG32 52 drivers/gpu/drm/radeon/ni.c r = RREG32(TN_SMC_IND_DATA_0); RREG32 671 drivers/gpu/drm/radeon/ni.c mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; RREG32 672 drivers/gpu/drm/radeon/ni.c running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; RREG32 676 drivers/gpu/drm/radeon/ni.c blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); RREG32 701 drivers/gpu/drm/radeon/ni.c if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) RREG32 873 drivers/gpu/drm/radeon/ni.c *val = RREG32(reg); RREG32 1019 drivers/gpu/drm/radeon/ni.c mc_shared_chmap = RREG32(MC_SHARED_CHMAP); RREG32 1020 drivers/gpu/drm/radeon/ni.c mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); RREG32 1097 drivers/gpu/drm/radeon/ni.c rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; RREG32 1117 drivers/gpu/drm/radeon/ni.c simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; RREG32 1166 drivers/gpu/drm/radeon/ni.c cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); RREG32 1174 drivers/gpu/drm/radeon/ni.c sx_debug_1 = RREG32(SX_DEBUG_1); RREG32 1178 drivers/gpu/drm/radeon/ni.c smx_dc_ctl0 = RREG32(SMX_DC_CTL0); RREG32 1240 drivers/gpu/drm/radeon/ni.c tmp = RREG32(HDP_MISC_CNTL); RREG32 1244 drivers/gpu/drm/radeon/ni.c hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); RREG32 1363 drivers/gpu/drm/radeon/ni.c rdev->vm_manager.saved_table_addr[i] = RREG32( RREG32 1483 drivers/gpu/drm/radeon/ni.c rptr = RREG32(CP_RB0_RPTR); RREG32 1485 drivers/gpu/drm/radeon/ni.c rptr = RREG32(CP_RB1_RPTR); RREG32 1487 drivers/gpu/drm/radeon/ni.c rptr = RREG32(CP_RB2_RPTR); RREG32 1499 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB0_WPTR); RREG32 1501 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB1_WPTR); RREG32 1503 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB2_WPTR); RREG32 1513 drivers/gpu/drm/radeon/ni.c (void)RREG32(CP_RB0_WPTR); RREG32 1516 drivers/gpu/drm/radeon/ni.c (void)RREG32(CP_RB1_WPTR); RREG32 1519 drivers/gpu/drm/radeon/ni.c (void)RREG32(CP_RB2_WPTR); RREG32 1671 drivers/gpu/drm/radeon/ni.c RREG32(GRBM_SOFT_RESET); RREG32 1674 drivers/gpu/drm/radeon/ni.c RREG32(GRBM_SOFT_RESET); RREG32 1752 drivers/gpu/drm/radeon/ni.c tmp = RREG32(GRBM_STATUS); RREG32 1769 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); RREG32 1774 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); RREG32 1779 drivers/gpu/drm/radeon/ni.c tmp = RREG32(SRBM_STATUS2); RREG32 1787 drivers/gpu/drm/radeon/ni.c tmp = RREG32(SRBM_STATUS); RREG32 1811 drivers/gpu/drm/radeon/ni.c tmp = RREG32(VM_L2_STATUS); RREG32 1837 drivers/gpu/drm/radeon/ni.c RREG32(0x14F8)); RREG32 1839 drivers/gpu/drm/radeon/ni.c RREG32(0x14D8)); RREG32 1841 drivers/gpu/drm/radeon/ni.c RREG32(0x14FC)); RREG32 1843 drivers/gpu/drm/radeon/ni.c RREG32(0x14DC)); RREG32 1850 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); RREG32 1857 drivers/gpu/drm/radeon/ni.c tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); RREG32 1920 drivers/gpu/drm/radeon/ni.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 1924 drivers/gpu/drm/radeon/ni.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 1930 drivers/gpu/drm/radeon/ni.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 1934 drivers/gpu/drm/radeon/ni.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 1938 drivers/gpu/drm/radeon/ni.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 1944 drivers/gpu/drm/radeon/ni.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 2512 drivers/gpu/drm/radeon/ni.c u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET); RREG32 2733 drivers/gpu/drm/radeon/ni.c if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) RREG32 2743 drivers/gpu/drm/radeon/ni.c if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) RREG32 66 drivers/gpu/drm/radeon/ni_dma.c rptr = RREG32(reg); RREG32 90 drivers/gpu/drm/radeon/ni_dma.c return (RREG32(reg) & 0x3fffc) >> 2; RREG32 166 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); RREG32 171 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); RREG32 239 drivers/gpu/drm/radeon/ni_dma.c dma_cntl = RREG32(DMA_CNTL + reg_offset); RREG32 1088 drivers/gpu/drm/radeon/ni_dpm.c tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK; RREG32 1185 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); RREG32 1186 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 1187 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 1188 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); RREG32 1189 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 1190 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 1191 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); RREG32 1192 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2); RREG32 1193 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); RREG32 1194 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2); RREG32 1195 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); RREG32 1196 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); RREG32 1197 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); RREG32 1198 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); RREG32 1210 drivers/gpu/drm/radeon/ni_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 1369 drivers/gpu/drm/radeon/ni_dpm.c u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK; RREG32 1516 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 1517 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 1518 drivers/gpu/drm/radeon/ni_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; RREG32 1521 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); RREG32 1522 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); RREG32 1523 drivers/gpu/drm/radeon/ni_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; RREG32 1526 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); RREG32 1527 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); RREG32 1528 drivers/gpu/drm/radeon/ni_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; RREG32 1531 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); RREG32 1532 drivers/gpu/drm/radeon/ni_dpm.c mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); RREG32 1533 drivers/gpu/drm/radeon/ni_dpm.c burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; RREG32 1564 drivers/gpu/drm/radeon/ni_dpm.c mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; RREG32 1628 drivers/gpu/drm/radeon/ni_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 1629 drivers/gpu/drm/radeon/ni_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 2189 drivers/gpu/drm/radeon/ni_dpm.c mc_seq_misc7 = RREG32(MC_SEQ_MISC7); RREG32 2319 drivers/gpu/drm/radeon/ni_dpm.c u32 tmp = RREG32(DC_STUTTER_CNTL); RREG32 2346 drivers/gpu/drm/radeon/ni_dpm.c ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) RREG32 2347 drivers/gpu/drm/radeon/ni_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 2349 drivers/gpu/drm/radeon/ni_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; RREG32 2721 drivers/gpu/drm/radeon/ni_dpm.c temp_reg = RREG32(MC_PMG_CMD_EMRS); RREG32 2732 drivers/gpu/drm/radeon/ni_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS); RREG32 2747 drivers/gpu/drm/radeon/ni_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS1); RREG32 2883 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); RREG32 2884 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); RREG32 2885 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); RREG32 2886 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); RREG32 2887 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); RREG32 2888 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); RREG32 2889 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); RREG32 2890 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); RREG32 2891 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); RREG32 2892 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); RREG32 2893 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); RREG32 2894 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); RREG32 2895 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); RREG32 3154 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK); RREG32 3354 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK | RREG32 3470 drivers/gpu/drm/radeon/ni_dpm.c bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; RREG32 3485 drivers/gpu/drm/radeon/ni_dpm.c bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK; RREG32 4312 drivers/gpu/drm/radeon/ni_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 4332 drivers/gpu/drm/radeon/ni_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 4350 drivers/gpu/drm/radeon/ni_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 80 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) RREG32 85 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) RREG32 97 drivers/gpu/drm/radeon/r100.c vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 98 drivers/gpu/drm/radeon/r100.c vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 100 drivers/gpu/drm/radeon/r100.c vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 101 drivers/gpu/drm/radeon/r100.c vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 125 drivers/gpu/drm/radeon/r100.c if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) RREG32 128 drivers/gpu/drm/radeon/r100.c if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) RREG32 174 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) RREG32 200 drivers/gpu/drm/radeon/r100.c return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RREG32 360 drivers/gpu/drm/radeon/r100.c tmp = RREG32(voltage->gpio.reg); RREG32 369 drivers/gpu/drm/radeon/r100.c tmp = RREG32(voltage->gpio.reg); RREG32 461 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 465 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CRTC_GEN_CNTL); RREG32 492 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 496 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CRTC_GEN_CNTL); RREG32 514 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) RREG32 536 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) RREG32 540 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) RREG32 565 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_FP_GEN_CNTL); RREG32 573 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_FP2_GEN_CNTL); RREG32 665 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; RREG32 672 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; RREG32 687 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; RREG32 741 drivers/gpu/drm/radeon/r100.c RREG32(RADEON_GEN_INT_CNTL); RREG32 753 drivers/gpu/drm/radeon/r100.c tmp = RREG32(R_000044_GEN_INT_STATUS); RREG32 759 drivers/gpu/drm/radeon/r100.c uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); RREG32 822 drivers/gpu/drm/radeon/r100.c msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; RREG32 837 drivers/gpu/drm/radeon/r100.c return RREG32(RADEON_CRTC_CRNT_FRAME); RREG32 839 drivers/gpu/drm/radeon/r100.c return RREG32(RADEON_CRTC2_CRNT_FRAME); RREG32 973 drivers/gpu/drm/radeon/r100.c tmp = RREG32(R_000E40_RBBM_STATUS); RREG32 1070 drivers/gpu/drm/radeon/r100.c rptr = RREG32(RADEON_CP_RB_RPTR); RREG32 1078 drivers/gpu/drm/radeon/r100.c return RREG32(RADEON_CP_RB_WPTR); RREG32 1085 drivers/gpu/drm/radeon/r100.c (void)RREG32(RADEON_CP_RB_WPTR); RREG32 2475 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; RREG32 2493 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_RBBM_STATUS); RREG32 2509 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_MC_STATUS); RREG32 2522 drivers/gpu/drm/radeon/r100.c rbbm_status = RREG32(R_000E40_RBBM_STATUS); RREG32 2535 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; RREG32 2544 drivers/gpu/drm/radeon/r100.c tmp = RREG32(R_000030_BUS_CNTL); RREG32 2550 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_BUS_CNTL); RREG32 2562 drivers/gpu/drm/radeon/r100.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 2567 drivers/gpu/drm/radeon/r100.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 2571 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_RB_CNTL); RREG32 2584 drivers/gpu/drm/radeon/r100.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 2588 drivers/gpu/drm/radeon/r100.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 2592 drivers/gpu/drm/radeon/r100.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 2596 drivers/gpu/drm/radeon/r100.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 2658 drivers/gpu/drm/radeon/r100.c u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); RREG32 2659 drivers/gpu/drm/radeon/r100.c u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 2660 drivers/gpu/drm/radeon/r100.c u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); RREG32 2706 drivers/gpu/drm/radeon/r100.c else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) RREG32 2711 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_MEM_CNTL); RREG32 2722 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_MEM_CNTL); RREG32 2739 drivers/gpu/drm/radeon/r100.c aper_size = RREG32(RADEON_CONFIG_APER_SIZE); RREG32 2767 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) RREG32 2783 drivers/gpu/drm/radeon/r100.c config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); RREG32 2787 drivers/gpu/drm/radeon/r100.c tom = RREG32(RADEON_NB_TOM); RREG32 2792 drivers/gpu/drm/radeon/r100.c rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); RREG32 2817 drivers/gpu/drm/radeon/r100.c temp = RREG32(RADEON_CONFIG_CNTL); RREG32 2835 drivers/gpu/drm/radeon/r100.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; RREG32 2850 drivers/gpu/drm/radeon/r100.c (void)RREG32(RADEON_CLOCK_CNTL_DATA); RREG32 2851 drivers/gpu/drm/radeon/r100.c (void)RREG32(RADEON_CRTC_GEN_CNTL); RREG32 2872 drivers/gpu/drm/radeon/r100.c save = RREG32(RADEON_CLOCK_CNTL_INDEX); RREG32 2875 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CLOCK_CNTL_DATA); RREG32 2888 drivers/gpu/drm/radeon/r100.c data = RREG32(RADEON_CLOCK_CNTL_DATA); RREG32 2931 drivers/gpu/drm/radeon/r100.c seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); RREG32 2932 drivers/gpu/drm/radeon/r100.c seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); RREG32 2933 drivers/gpu/drm/radeon/r100.c seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); RREG32 2936 drivers/gpu/drm/radeon/r100.c reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; RREG32 2938 drivers/gpu/drm/radeon/r100.c value = RREG32(RADEON_RBBM_CMDFIFO_DATA); RREG32 2954 drivers/gpu/drm/radeon/r100.c rdp = RREG32(RADEON_CP_RB_RPTR); RREG32 2955 drivers/gpu/drm/radeon/r100.c wdp = RREG32(RADEON_CP_RB_WPTR); RREG32 2957 drivers/gpu/drm/radeon/r100.c seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); RREG32 2981 drivers/gpu/drm/radeon/r100.c seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); RREG32 2982 drivers/gpu/drm/radeon/r100.c seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); RREG32 2983 drivers/gpu/drm/radeon/r100.c csq_stat = RREG32(RADEON_CP_CSQ_STAT); RREG32 2984 drivers/gpu/drm/radeon/r100.c csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); RREG32 3004 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_CSQ_DATA); RREG32 3010 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_CSQ_DATA); RREG32 3016 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_CSQ_DATA); RREG32 3029 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CONFIG_MEMSIZE); RREG32 3031 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_MC_FB_LOCATION); RREG32 3033 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_BUS_CNTL); RREG32 3035 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_MC_AGP_LOCATION); RREG32 3037 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AGP_BASE); RREG32 3039 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_HOST_PATH_CNTL); RREG32 3041 drivers/gpu/drm/radeon/r100.c tmp = RREG32(0x01D0); RREG32 3043 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AIC_LO_ADDR); RREG32 3045 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_AIC_HI_ADDR); RREG32 3047 drivers/gpu/drm/radeon/r100.c tmp = RREG32(0x01E4); RREG32 3247 drivers/gpu/drm/radeon/r100.c uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); RREG32 3293 drivers/gpu/drm/radeon/r100.c temp = RREG32(RADEON_MEM_TIMING_CNTL); RREG32 3333 drivers/gpu/drm/radeon/r100.c temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); RREG32 3354 drivers/gpu/drm/radeon/r100.c temp = RREG32(RADEON_MEM_CNTL); RREG32 3358 drivers/gpu/drm/radeon/r100.c temp = RREG32(R300_MC_IND_INDEX); RREG32 3362 drivers/gpu/drm/radeon/r100.c temp = RREG32(R300_MC_IND_DATA); RREG32 3365 drivers/gpu/drm/radeon/r100.c temp = RREG32(R300_MC_READ_CNTL_AB); RREG32 3369 drivers/gpu/drm/radeon/r100.c temp = RREG32(R300_MC_READ_CNTL_AB); RREG32 3505 drivers/gpu/drm/radeon/r100.c temp = RREG32(RADEON_GRPH_BUFFER_CNTL); RREG32 3528 drivers/gpu/drm/radeon/r100.c temp = RREG32(RS400_DISP1_REG_CNTL); RREG32 3534 drivers/gpu/drm/radeon/r100.c temp = RREG32(RS400_DMIF_MEM_CNTL1); RREG32 3545 drivers/gpu/drm/radeon/r100.c (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); RREG32 3561 drivers/gpu/drm/radeon/r100.c grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); RREG32 3620 drivers/gpu/drm/radeon/r100.c temp = RREG32(RS400_DISP2_REQ_CNTL1); RREG32 3626 drivers/gpu/drm/radeon/r100.c temp = RREG32(RS400_DISP2_REQ_CNTL2); RREG32 3640 drivers/gpu/drm/radeon/r100.c (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); RREG32 3674 drivers/gpu/drm/radeon/r100.c tmp = RREG32(scratch); RREG32 3751 drivers/gpu/drm/radeon/r100.c tmp = RREG32(scratch); RREG32 3781 drivers/gpu/drm/radeon/r100.c save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); RREG32 3782 drivers/gpu/drm/radeon/r100.c save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); RREG32 3783 drivers/gpu/drm/radeon/r100.c save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); RREG32 3785 drivers/gpu/drm/radeon/r100.c save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); RREG32 3786 drivers/gpu/drm/radeon/r100.c save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); RREG32 3799 drivers/gpu/drm/radeon/r100.c C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); RREG32 3928 drivers/gpu/drm/radeon/r100.c rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 3957 drivers/gpu/drm/radeon/r100.c RREG32(R_000E40_RBBM_STATUS), RREG32 3958 drivers/gpu/drm/radeon/r100.c RREG32(R_0007C0_CP_STAT)); RREG32 4015 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_CSQ_CNTL); RREG32 4019 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_CP_RB_CNTL); RREG32 4023 drivers/gpu/drm/radeon/r100.c tmp = RREG32(RADEON_SCRATCH_UMSK); RREG32 4061 drivers/gpu/drm/radeon/r100.c RREG32(R_000E40_RBBM_STATUS), RREG32 4062 drivers/gpu/drm/radeon/r100.c RREG32(R_0007C0_CP_STAT)); RREG32 68 drivers/gpu/drm/radeon/r300.c r = RREG32(RADEON_PCIE_DATA); RREG32 343 drivers/gpu/drm/radeon/r300.c (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { RREG32 355 drivers/gpu/drm/radeon/r300.c tmp = RREG32(RADEON_MC_STATUS); RREG32 399 drivers/gpu/drm/radeon/r300.c tmp = RREG32(R300_DST_PIPE_CONFIG); RREG32 422 drivers/gpu/drm/radeon/r300.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 427 drivers/gpu/drm/radeon/r300.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 431 drivers/gpu/drm/radeon/r300.c tmp = RREG32(RADEON_CP_RB_CNTL); RREG32 442 drivers/gpu/drm/radeon/r300.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 446 drivers/gpu/drm/radeon/r300.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 454 drivers/gpu/drm/radeon/r300.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 458 drivers/gpu/drm/radeon/r300.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 483 drivers/gpu/drm/radeon/r300.c tmp = RREG32(RADEON_MEM_CNTL); RREG32 494 drivers/gpu/drm/radeon/r300.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; RREG32 1428 drivers/gpu/drm/radeon/r300.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 1459 drivers/gpu/drm/radeon/r300.c RREG32(R_000E40_RBBM_STATUS), RREG32 1460 drivers/gpu/drm/radeon/r300.c RREG32(R_0007C0_CP_STAT)); RREG32 1540 drivers/gpu/drm/radeon/r300.c RREG32(R_000E40_RBBM_STATUS), RREG32 1541 drivers/gpu/drm/radeon/r300.c RREG32(R_0007C0_CP_STAT)); RREG32 104 drivers/gpu/drm/radeon/r420.c gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); RREG32 140 drivers/gpu/drm/radeon/r420.c tmp = RREG32(R300_DST_PIPE_CONFIG); RREG32 144 drivers/gpu/drm/radeon/r420.c RREG32(R300_RB2D_DSTCACHE_MODE) | RREG32 153 drivers/gpu/drm/radeon/r420.c tmp = RREG32(RV530_GB_PIPE_SELECT2); RREG32 172 drivers/gpu/drm/radeon/r420.c r = RREG32(R_0001FC_MC_IND_DATA); RREG32 290 drivers/gpu/drm/radeon/r420.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 322 drivers/gpu/drm/radeon/r420.c RREG32(R_000E40_RBBM_STATUS), RREG32 323 drivers/gpu/drm/radeon/r420.c RREG32(R_0007C0_CP_STAT)); RREG32 413 drivers/gpu/drm/radeon/r420.c RREG32(R_000E40_RBBM_STATUS), RREG32 414 drivers/gpu/drm/radeon/r420.c RREG32(R_0007C0_CP_STAT)); RREG32 490 drivers/gpu/drm/radeon/r420.c tmp = RREG32(R400_GB_PIPE_SELECT); RREG32 492 drivers/gpu/drm/radeon/r420.c tmp = RREG32(R300_GB_TILE_CONFIG); RREG32 494 drivers/gpu/drm/radeon/r420.c tmp = RREG32(R300_DST_PIPE_CONFIG); RREG32 82 drivers/gpu/drm/radeon/r520.c gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); RREG32 83 drivers/gpu/drm/radeon/r520.c tmp = RREG32(R300_DST_PIPE_CONFIG); RREG32 203 drivers/gpu/drm/radeon/r520.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 232 drivers/gpu/drm/radeon/r520.c RREG32(R_000E40_RBBM_STATUS), RREG32 233 drivers/gpu/drm/radeon/r520.c RREG32(R_0007C0_CP_STAT)); RREG32 278 drivers/gpu/drm/radeon/r520.c RREG32(R_000E40_RBBM_STATUS), RREG32 279 drivers/gpu/drm/radeon/r520.c RREG32(R_0007C0_CP_STAT)); RREG32 127 drivers/gpu/drm/radeon/r600.c r = RREG32(R600_RCU_DATA); RREG32 149 drivers/gpu/drm/radeon/r600.c r = RREG32(R600_UVD_CTX_DATA); RREG32 183 drivers/gpu/drm/radeon/r600.c *val = RREG32(reg); RREG32 352 drivers/gpu/drm/radeon/r600.c u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> RREG32 797 drivers/gpu/drm/radeon/r600.c if (RREG32(GRBM_STATUS) & GUI_ACTIVE) RREG32 811 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) RREG32 815 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) RREG32 819 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) RREG32 823 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) RREG32 828 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) RREG32 832 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) RREG32 841 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) RREG32 845 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) RREG32 849 drivers/gpu/drm/radeon/r600.c if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) RREG32 868 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD1_INT_CONTROL); RREG32 876 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD2_INT_CONTROL); RREG32 884 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD3_INT_CONTROL); RREG32 892 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD4_INT_CONTROL); RREG32 900 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD5_INT_CONTROL); RREG32 909 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD6_INT_CONTROL); RREG32 922 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); RREG32 930 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); RREG32 938 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); RREG32 1100 drivers/gpu/drm/radeon/r600.c tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); RREG32 1270 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; RREG32 1285 drivers/gpu/drm/radeon/r600.c r = RREG32(R_0028FC_MC_DATA); RREG32 1425 drivers/gpu/drm/radeon/r600.c base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; RREG32 1443 drivers/gpu/drm/radeon/r600.c tmp = RREG32(RAMCFG); RREG32 1451 drivers/gpu/drm/radeon/r600.c tmp = RREG32(CHMAP); RREG32 1472 drivers/gpu/drm/radeon/r600.c rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 1473 drivers/gpu/drm/radeon/r600.c rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 1557 drivers/gpu/drm/radeon/r600.c u32 tmp = RREG32(R600_BIOS_3_SCRATCH); RREG32 1570 drivers/gpu/drm/radeon/r600.c RREG32(R_008010_GRBM_STATUS)); RREG32 1572 drivers/gpu/drm/radeon/r600.c RREG32(R_008014_GRBM_STATUS2)); RREG32 1574 drivers/gpu/drm/radeon/r600.c RREG32(R_000E50_SRBM_STATUS)); RREG32 1576 drivers/gpu/drm/radeon/r600.c RREG32(CP_STALLED_STAT1)); RREG32 1578 drivers/gpu/drm/radeon/r600.c RREG32(CP_STALLED_STAT2)); RREG32 1580 drivers/gpu/drm/radeon/r600.c RREG32(CP_BUSY_STAT)); RREG32 1582 drivers/gpu/drm/radeon/r600.c RREG32(CP_STAT)); RREG32 1584 drivers/gpu/drm/radeon/r600.c RREG32(DMA_STATUS_REG)); RREG32 1594 drivers/gpu/drm/radeon/r600.c if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { RREG32 1595 drivers/gpu/drm/radeon/r600.c crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 1603 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); RREG32 1622 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_008010_GRBM_STATUS); RREG32 1647 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DMA_STATUS_REG); RREG32 1652 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_000E50_SRBM_STATUS); RREG32 1709 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DMA_RB_CNTL); RREG32 1785 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_008020_GRBM_SOFT_RESET); RREG32 1789 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_008020_GRBM_SOFT_RESET); RREG32 1795 drivers/gpu/drm/radeon/r600.c tmp = RREG32(R_008020_GRBM_SOFT_RESET); RREG32 1799 drivers/gpu/drm/radeon/r600.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 1803 drivers/gpu/drm/radeon/r600.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 1809 drivers/gpu/drm/radeon/r600.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 1840 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DMA_RB_CNTL); RREG32 1858 drivers/gpu/drm/radeon/r600.c tmp = RREG32(BUS_CNTL); RREG32 1862 drivers/gpu/drm/radeon/r600.c tmp = RREG32(BIF_SCRATCH0); RREG32 1876 drivers/gpu/drm/radeon/r600.c if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) RREG32 2088 drivers/gpu/drm/radeon/r600.c ramcfg = RREG32(RAMCFG); RREG32 2120 drivers/gpu/drm/radeon/r600.c cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; RREG32 2125 drivers/gpu/drm/radeon/r600.c disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; RREG32 2160 drivers/gpu/drm/radeon/r600.c tmp = RREG32(SX_DEBUG_1); RREG32 2185 drivers/gpu/drm/radeon/r600.c tmp = RREG32(SQ_MS_FIFO_SIZES); RREG32 2204 drivers/gpu/drm/radeon/r600.c sq_config = RREG32(SQ_CONFIG); RREG32 2378 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDP_HOST_PATH_CNTL); RREG32 2381 drivers/gpu/drm/radeon/r600.c tmp = RREG32(ARB_POP); RREG32 2403 drivers/gpu/drm/radeon/r600.c (void)RREG32(PCIE_PORT_INDEX); RREG32 2404 drivers/gpu/drm/radeon/r600.c r = RREG32(PCIE_PORT_DATA); RREG32 2415 drivers/gpu/drm/radeon/r600.c (void)RREG32(PCIE_PORT_INDEX); RREG32 2417 drivers/gpu/drm/radeon/r600.c (void)RREG32(PCIE_PORT_DATA); RREG32 2625 drivers/gpu/drm/radeon/r600.c rptr = RREG32(R600_CP_RB_RPTR); RREG32 2633 drivers/gpu/drm/radeon/r600.c return RREG32(R600_CP_RB_WPTR); RREG32 2640 drivers/gpu/drm/radeon/r600.c (void)RREG32(R600_CP_RB_WPTR); RREG32 2661 drivers/gpu/drm/radeon/r600.c RREG32(GRBM_SOFT_RESET); RREG32 2724 drivers/gpu/drm/radeon/r600.c RREG32(GRBM_SOFT_RESET); RREG32 2846 drivers/gpu/drm/radeon/r600.c tmp = RREG32(scratch); RREG32 3193 drivers/gpu/drm/radeon/r600.c temp = RREG32(CONFIG_CNTL); RREG32 3439 drivers/gpu/drm/radeon/r600.c tmp = RREG32(scratch); RREG32 3540 drivers/gpu/drm/radeon/r600.c RREG32(SRBM_SOFT_RESET); RREG32 3543 drivers/gpu/drm/radeon/r600.c RREG32(SRBM_SOFT_RESET); RREG32 3595 drivers/gpu/drm/radeon/r600.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 3596 drivers/gpu/drm/radeon/r600.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 3607 drivers/gpu/drm/radeon/r600.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 3608 drivers/gpu/drm/radeon/r600.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 3626 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; RREG32 3635 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3637 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3639 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3641 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3644 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3646 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; RREG32 3648 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3650 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3653 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3655 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3661 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; RREG32 3663 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; RREG32 3665 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; RREG32 3667 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3669 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3701 drivers/gpu/drm/radeon/r600.c interrupt_cntl = RREG32(INTERRUPT_CNTL); RREG32 3787 drivers/gpu/drm/radeon/r600.c hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3788 drivers/gpu/drm/radeon/r600.c hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3789 drivers/gpu/drm/radeon/r600.c hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3790 drivers/gpu/drm/radeon/r600.c hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3792 drivers/gpu/drm/radeon/r600.c hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3793 drivers/gpu/drm/radeon/r600.c hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3794 drivers/gpu/drm/radeon/r600.c hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; RREG32 3795 drivers/gpu/drm/radeon/r600.c hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; RREG32 3797 drivers/gpu/drm/radeon/r600.c hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3798 drivers/gpu/drm/radeon/r600.c hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3801 drivers/gpu/drm/radeon/r600.c hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3802 drivers/gpu/drm/radeon/r600.c hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3803 drivers/gpu/drm/radeon/r600.c hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; RREG32 3804 drivers/gpu/drm/radeon/r600.c hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3805 drivers/gpu/drm/radeon/r600.c hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; RREG32 3808 drivers/gpu/drm/radeon/r600.c dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; RREG32 3811 drivers/gpu/drm/radeon/r600.c thermal_int = RREG32(CG_THERMAL_INT) & RREG32 3814 drivers/gpu/drm/radeon/r600.c thermal_int = RREG32(RV770_CG_THERMAL_INT) & RREG32 3910 drivers/gpu/drm/radeon/r600.c RREG32(R_000E50_SRBM_STATUS); RREG32 3920 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); RREG32 3921 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); RREG32 3922 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); RREG32 3924 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); RREG32 3925 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); RREG32 3927 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); RREG32 3928 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); RREG32 3931 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); RREG32 3932 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); RREG32 3934 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); RREG32 3935 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); RREG32 3937 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); RREG32 3938 drivers/gpu/drm/radeon/r600.c rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); RREG32 3954 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD1_INT_CONTROL); RREG32 3958 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); RREG32 3965 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD2_INT_CONTROL); RREG32 3969 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); RREG32 3976 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD3_INT_CONTROL); RREG32 3980 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); RREG32 3986 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD4_INT_CONTROL); RREG32 3992 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD5_INT_CONTROL); RREG32 3997 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DC_HPD6_INT_CONTROL); RREG32 4002 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); RREG32 4007 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); RREG32 4013 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); RREG32 4019 drivers/gpu/drm/radeon/r600.c tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); RREG32 4023 drivers/gpu/drm/radeon/r600.c tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); RREG32 4047 drivers/gpu/drm/radeon/r600.c wptr = RREG32(IH_RB_WPTR); RREG32 4058 drivers/gpu/drm/radeon/r600.c tmp = RREG32(IH_RB_CNTL); RREG32 4110 drivers/gpu/drm/radeon/r600.c RREG32(IH_RB_WPTR); RREG32 4555 drivers/gpu/drm/radeon/r600.c link_cntl2 = RREG32(0x4088); RREG32 4569 drivers/gpu/drm/radeon/r600.c tmp = RREG32(0x541c); RREG32 4619 drivers/gpu/drm/radeon/r600.c clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | RREG32 4620 drivers/gpu/drm/radeon/r600.c ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 59 drivers/gpu/drm/radeon/r600_dma.c rptr = RREG32(DMA_RB_RPTR); RREG32 75 drivers/gpu/drm/radeon/r600_dma.c return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; RREG32 101 drivers/gpu/drm/radeon/r600_dma.c u32 rb_cntl = RREG32(DMA_RB_CNTL); RREG32 160 drivers/gpu/drm/radeon/r600_dma.c dma_cntl = RREG32(DMA_CNTL); RREG32 254 drivers/gpu/drm/radeon/r600_dpm.c if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1) RREG32 262 drivers/gpu/drm/radeon/r600_dpm.c RREG32(GRBM_PWR_CNTL); RREG32 297 drivers/gpu/drm/radeon/r600_dpm.c if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) RREG32 332 drivers/gpu/drm/radeon/r600_dpm.c if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) RREG32 538 drivers/gpu/drm/radeon/r600_dpm.c tmp = RREG32(VID_UPPER_GPIO_CNTL); RREG32 548 drivers/gpu/drm/radeon/r600_dpm.c gpio = RREG32(GPIOPAD_MASK); RREG32 552 drivers/gpu/drm/radeon/r600_dpm.c gpio = RREG32(GPIOPAD_EN); RREG32 556 drivers/gpu/drm/radeon/r600_dpm.c gpio = RREG32(GPIOPAD_A); RREG32 628 drivers/gpu/drm/radeon/r600_dpm.c tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK; RREG32 637 drivers/gpu/drm/radeon/r600_dpm.c tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK; RREG32 64 drivers/gpu/drm/radeon/r600_hdmi.c value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); RREG32 100 drivers/gpu/drm/radeon/r600_hdmi.c value = RREG32(R600_AUDIO_STATUS_BITS); RREG32 145 drivers/gpu/drm/radeon/r600_hdmi.c u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); RREG32 270 drivers/gpu/drm/radeon/r600_hdmi.c return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; RREG32 448 drivers/gpu/drm/radeon/r600_hdmi.c value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); RREG32 2544 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32(reg); \ RREG32 169 drivers/gpu/drm/radeon/radeon_agp.c agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; RREG32 257 drivers/gpu/drm/radeon/radeon_agp.c WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); RREG32 4082 drivers/gpu/drm/radeon/radeon_atombios.c bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); RREG32 4083 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); RREG32 4085 drivers/gpu/drm/radeon/radeon_atombios.c bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); RREG32 4086 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 4120 drivers/gpu/drm/radeon/radeon_atombios.c rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); RREG32 4144 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); RREG32 4146 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 4176 drivers/gpu/drm/radeon/radeon_atombios.c bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); RREG32 4177 drivers/gpu/drm/radeon/radeon_atombios.c bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); RREG32 4178 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); RREG32 4180 drivers/gpu/drm/radeon/radeon_atombios.c bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); RREG32 4181 drivers/gpu/drm/radeon/radeon_atombios.c bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); RREG32 4182 drivers/gpu/drm/radeon/radeon_atombios.c bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 4361 drivers/gpu/drm/radeon/radeon_atombios.c bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); RREG32 4363 drivers/gpu/drm/radeon/radeon_atombios.c bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); RREG32 4416 drivers/gpu/drm/radeon/radeon_atombios.c bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); RREG32 4418 drivers/gpu/drm/radeon/radeon_atombios.c bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); RREG32 119 drivers/gpu/drm/radeon/radeon_audio.c return RREG32(reg); RREG32 260 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(R600_BUS_CNTL); RREG32 261 drivers/gpu/drm/radeon/radeon_bios.c d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); RREG32 262 drivers/gpu/drm/radeon/radeon_bios.c d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); RREG32 263 drivers/gpu/drm/radeon/radeon_bios.c vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); RREG32 264 drivers/gpu/drm/radeon/radeon_bios.c rom_cntl = RREG32(R600_ROM_CNTL); RREG32 306 drivers/gpu/drm/radeon/radeon_bios.c viph_control = RREG32(RADEON_VIPH_CONTROL); RREG32 307 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(R600_BUS_CNTL); RREG32 308 drivers/gpu/drm/radeon/radeon_bios.c d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); RREG32 309 drivers/gpu/drm/radeon/radeon_bios.c d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); RREG32 310 drivers/gpu/drm/radeon/radeon_bios.c vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); RREG32 311 drivers/gpu/drm/radeon/radeon_bios.c rom_cntl = RREG32(R600_ROM_CNTL); RREG32 328 drivers/gpu/drm/radeon/radeon_bios.c cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); RREG32 337 drivers/gpu/drm/radeon/radeon_bios.c cg_spll_status = RREG32(R600_CG_SPLL_STATUS); RREG32 352 drivers/gpu/drm/radeon/radeon_bios.c cg_spll_status = RREG32(R600_CG_SPLL_STATUS); RREG32 379 drivers/gpu/drm/radeon/radeon_bios.c viph_control = RREG32(RADEON_VIPH_CONTROL); RREG32 380 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(R600_BUS_CNTL); RREG32 381 drivers/gpu/drm/radeon/radeon_bios.c d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); RREG32 382 drivers/gpu/drm/radeon/radeon_bios.c d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); RREG32 383 drivers/gpu/drm/radeon/radeon_bios.c vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); RREG32 384 drivers/gpu/drm/radeon/radeon_bios.c rom_cntl = RREG32(R600_ROM_CNTL); RREG32 385 drivers/gpu/drm/radeon/radeon_bios.c general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); RREG32 386 drivers/gpu/drm/radeon/radeon_bios.c low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); RREG32 387 drivers/gpu/drm/radeon/radeon_bios.c medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); RREG32 388 drivers/gpu/drm/radeon/radeon_bios.c high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); RREG32 389 drivers/gpu/drm/radeon/radeon_bios.c ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); RREG32 390 drivers/gpu/drm/radeon/radeon_bios.c lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); RREG32 453 drivers/gpu/drm/radeon/radeon_bios.c seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); RREG32 454 drivers/gpu/drm/radeon/radeon_bios.c viph_control = RREG32(RADEON_VIPH_CONTROL); RREG32 455 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(RV370_BUS_CNTL); RREG32 456 drivers/gpu/drm/radeon/radeon_bios.c d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); RREG32 457 drivers/gpu/drm/radeon/radeon_bios.c d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); RREG32 458 drivers/gpu/drm/radeon/radeon_bios.c vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); RREG32 459 drivers/gpu/drm/radeon/radeon_bios.c gpiopad_a = RREG32(RADEON_GPIOPAD_A); RREG32 460 drivers/gpu/drm/radeon/radeon_bios.c gpiopad_en = RREG32(RADEON_GPIOPAD_EN); RREG32 461 drivers/gpu/drm/radeon/radeon_bios.c gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); RREG32 512 drivers/gpu/drm/radeon/radeon_bios.c seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); RREG32 513 drivers/gpu/drm/radeon/radeon_bios.c viph_control = RREG32(RADEON_VIPH_CONTROL); RREG32 515 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(RV370_BUS_CNTL); RREG32 517 drivers/gpu/drm/radeon/radeon_bios.c bus_cntl = RREG32(RADEON_BUS_CNTL); RREG32 518 drivers/gpu/drm/radeon/radeon_bios.c crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); RREG32 520 drivers/gpu/drm/radeon/radeon_bios.c crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); RREG32 524 drivers/gpu/drm/radeon/radeon_bios.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 528 drivers/gpu/drm/radeon/radeon_bios.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 482 drivers/gpu/drm/radeon/radeon_clocks.c if ((RREG32(RADEON_CONFIG_CNTL) & RREG32 621 drivers/gpu/drm/radeon/radeon_clocks.c if (RREG32(RADEON_MEM_CNTL) & RREG32 674 drivers/gpu/drm/radeon/radeon_clocks.c ((RREG32(RADEON_CONFIG_CNTL) & RREG32 679 drivers/gpu/drm/radeon/radeon_clocks.c ((RREG32(RADEON_CONFIG_CNTL) & RREG32 697 drivers/gpu/drm/radeon/radeon_clocks.c ((RREG32(RADEON_CONFIG_CNTL) & RREG32 709 drivers/gpu/drm/radeon/radeon_clocks.c ((RREG32(RADEON_CONFIG_CNTL) & RREG32 1109 drivers/gpu/drm/radeon/radeon_combios.c uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); RREG32 1116 drivers/gpu/drm/radeon/radeon_combios.c fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); RREG32 1117 drivers/gpu/drm/radeon/radeon_combios.c fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); RREG32 1123 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); RREG32 1133 drivers/gpu/drm/radeon/radeon_combios.c (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; RREG32 1141 drivers/gpu/drm/radeon/radeon_combios.c ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; RREG32 2922 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); RREG32 2976 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); RREG32 3043 drivers/gpu/drm/radeon/radeon_combios.c tmp = RREG32(addr); RREG32 3053 drivers/gpu/drm/radeon/radeon_combios.c tmp = RREG32(addr); RREG32 3078 drivers/gpu/drm/radeon/radeon_combios.c if ((RREG32(RADEON_MC_STATUS) & RREG32 3206 drivers/gpu/drm/radeon/radeon_combios.c if ((RREG32(RADEON_MEM_STR_CNTL) & RREG32 3215 drivers/gpu/drm/radeon/radeon_combios.c tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); RREG32 3221 drivers/gpu/drm/radeon/radeon_combios.c tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); RREG32 3239 drivers/gpu/drm/radeon/radeon_combios.c mem_cntl = RREG32(RADEON_MEM_CNTL); RREG32 3246 drivers/gpu/drm/radeon/radeon_combios.c RREG32(RADEON_MEM_CNTL); RREG32 3422 drivers/gpu/drm/radeon/radeon_combios.c bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); RREG32 3423 drivers/gpu/drm/radeon/radeon_combios.c bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 3424 drivers/gpu/drm/radeon/radeon_combios.c bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); RREG32 3447 drivers/gpu/drm/radeon/radeon_combios.c bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 3467 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); RREG32 3468 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); RREG32 3566 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); RREG32 3601 drivers/gpu/drm/radeon/radeon_combios.c uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 39 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); RREG32 46 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); RREG32 53 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); RREG32 219 drivers/gpu/drm/radeon/radeon_device.c tmp = RREG32(reg); RREG32 675 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | RREG32 676 drivers/gpu/drm/radeon/radeon_device.c RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); RREG32 678 drivers/gpu/drm/radeon/radeon_device.c reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | RREG32 679 drivers/gpu/drm/radeon/radeon_device.c RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); RREG32 682 drivers/gpu/drm/radeon/radeon_device.c reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | RREG32 683 drivers/gpu/drm/radeon/radeon_device.c RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); RREG32 688 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(AVIVO_D1CRTC_CONTROL) | RREG32 689 drivers/gpu/drm/radeon/radeon_device.c RREG32(AVIVO_D2CRTC_CONTROL); RREG32 694 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(RADEON_CRTC_GEN_CNTL) | RREG32 695 drivers/gpu/drm/radeon/radeon_device.c RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 704 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(R600_CONFIG_MEMSIZE); RREG32 706 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(RADEON_CONFIG_MEMSIZE); RREG32 925 drivers/gpu/drm/radeon/radeon_device.c r = RREG32(reg*4); RREG32 201 drivers/gpu/drm/radeon/radeon_display.c dac2_cntl = RREG32(RADEON_DAC_CNTL2); RREG32 1831 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1833 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1838 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1840 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1845 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1847 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1852 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1854 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1859 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1861 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1866 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + RREG32 1868 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + RREG32 1874 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); RREG32 1875 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); RREG32 1879 drivers/gpu/drm/radeon/radeon_display.c vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); RREG32 1880 drivers/gpu/drm/radeon/radeon_display.c position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); RREG32 1889 drivers/gpu/drm/radeon/radeon_display.c vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & RREG32 1892 drivers/gpu/drm/radeon/radeon_display.c position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 1893 drivers/gpu/drm/radeon/radeon_display.c stat_crtc = RREG32(RADEON_CRTC_STATUS); RREG32 1900 drivers/gpu/drm/radeon/radeon_display.c vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & RREG32 1902 drivers/gpu/drm/radeon/radeon_display.c position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; RREG32 1903 drivers/gpu/drm/radeon/radeon_display.c stat_crtc = RREG32(RADEON_CRTC2_STATUS); RREG32 99 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(chan->rec.mask_clk_reg); RREG32 104 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(AUX_CONTROL + aux_offset[instance]); RREG32 153 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); RREG32 182 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); RREG32 186 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); RREG32 38 drivers/gpu/drm/radeon/radeon_dp_mst.c reg = RREG32(NI_DIG_BE_CNTL + primary->offset); RREG32 57 drivers/gpu/drm/radeon/radeon_dp_mst.c temp = RREG32(NI_DIG_FE_CNTL + offset); RREG32 79 drivers/gpu/drm/radeon/radeon_dp_mst.c temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); RREG32 97 drivers/gpu/drm/radeon/radeon_dp_mst.c temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); RREG32 180 drivers/gpu/drm/radeon/radeon_dp_mst.c temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); RREG32 101 drivers/gpu/drm/radeon/radeon_fence.c seq = RREG32(drv->scratch_reg); RREG32 132 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 138 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; RREG32 141 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; RREG32 145 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; RREG32 148 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; RREG32 152 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; RREG32 154 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 156 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; RREG32 158 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_data_reg); RREG32 171 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; RREG32 173 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); RREG32 175 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; RREG32 177 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_data_reg); RREG32 190 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->y_clk_reg); RREG32 205 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->y_data_reg); RREG32 219 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; RREG32 232 drivers/gpu/drm/radeon/radeon_i2c.c val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; RREG32 354 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 482 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 485 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 514 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 517 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 527 drivers/gpu/drm/radeon/radeon_i2c.c p->buf[j] = RREG32(i2c_data) & 0xff; RREG32 542 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 545 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(i2c_cntl_0); RREG32 568 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 601 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_clk_reg); RREG32 604 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_clk_reg); RREG32 606 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_data_reg); RREG32 609 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_data_reg); RREG32 612 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->a_clk_reg); RREG32 615 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->a_clk_reg); RREG32 617 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->a_data_reg); RREG32 620 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->a_data_reg); RREG32 623 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->en_clk_reg); RREG32 626 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->en_clk_reg); RREG32 628 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->en_data_reg); RREG32 631 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->en_data_reg); RREG32 634 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 636 drivers/gpu/drm/radeon/radeon_i2c.c saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); RREG32 637 drivers/gpu/drm/radeon/radeon_i2c.c saved2 = RREG32(0x494); RREG32 643 drivers/gpu/drm/radeon/radeon_i2c.c if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) RREG32 690 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 693 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 732 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 735 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 746 drivers/gpu/drm/radeon/radeon_i2c.c p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; RREG32 775 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 778 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(AVIVO_DC_I2C_STATUS1); RREG32 805 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(RADEON_BIOS_6_SCRATCH); RREG32 572 drivers/gpu/drm/radeon/radeon_irq_kms.c u32 tmp = RREG32(reg); RREG32 68 drivers/gpu/drm/radeon/radeon_legacy_crtc.c fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & RREG32 71 drivers/gpu/drm/radeon/radeon_legacy_crtc.c fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & RREG32 538 drivers/gpu/drm/radeon/radeon_legacy_crtc.c gen_cntl_val = RREG32(gen_cntl_reg); RREG32 655 drivers/gpu/drm/radeon/radeon_legacy_crtc.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; RREG32 675 drivers/gpu/drm/radeon/radeon_legacy_crtc.c disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); RREG32 688 drivers/gpu/drm/radeon/radeon_legacy_crtc.c crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; RREG32 706 drivers/gpu/drm/radeon/radeon_legacy_crtc.c crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); RREG32 712 drivers/gpu/drm/radeon/radeon_legacy_crtc.c disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); RREG32 64 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); RREG32 92 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); RREG32 95 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); RREG32 100 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); RREG32 195 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); RREG32 198 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); RREG32 205 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); RREG32 216 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); RREG32 286 drivers/gpu/drm/radeon/radeon_legacy_encoders.c backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> RREG32 360 drivers/gpu/drm/radeon/radeon_legacy_encoders.c backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> RREG32 411 drivers/gpu/drm/radeon/radeon_legacy_encoders.c backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> RREG32 523 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); RREG32 524 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); RREG32 525 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); RREG32 598 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & RREG32 602 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); RREG32 607 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & RREG32 612 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; RREG32 631 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); RREG32 661 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); RREG32 662 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); RREG32 663 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_cntl = RREG32(RADEON_DAC_CNTL); RREG32 664 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); RREG32 703 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) RREG32 735 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); RREG32 794 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); RREG32 825 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & RREG32 835 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | RREG32 899 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 961 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 963 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 1051 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 1054 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); RREG32 1056 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 1057 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 1170 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 1214 drivers/gpu/drm/radeon/radeon_legacy_encoders.c gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; RREG32 1215 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); RREG32 1217 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); RREG32 1219 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 1222 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); RREG32 1227 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_cntl = RREG32(RADEON_DAC_CNTL); RREG32 1232 drivers/gpu/drm/radeon/radeon_legacy_encoders.c gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; RREG32 1234 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; RREG32 1260 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; RREG32 1316 drivers/gpu/drm/radeon/radeon_legacy_encoders.c gpiopad_a = RREG32(RADEON_GPIOPAD_A); RREG32 1317 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_cntl2 = RREG32(RADEON_DAC_CNTL2); RREG32 1318 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 1319 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); RREG32 1320 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 1321 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); RREG32 1345 drivers/gpu/drm/radeon/radeon_legacy_encoders.c RREG32(RADEON_TV_DAC_CNTL); RREG32 1356 drivers/gpu/drm/radeon/radeon_legacy_encoders.c RREG32(RADEON_TV_DAC_CNTL); RREG32 1359 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmp = RREG32(RADEON_TV_DAC_CNTL); RREG32 1389 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_cntl2 = RREG32(RADEON_DAC_CNTL2); RREG32 1390 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); RREG32 1391 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 1392 drivers/gpu/drm/radeon/radeon_legacy_encoders.c config_cntl = RREG32(RADEON_CONFIG_CNTL); RREG32 1393 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); RREG32 1425 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmp = RREG32(RADEON_TV_DAC_CNTL); RREG32 1455 drivers/gpu/drm/radeon/radeon_legacy_encoders.c gpio_monid = RREG32(RADEON_GPIO_MONID); RREG32 1456 drivers/gpu/drm/radeon/radeon_legacy_encoders.c fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); RREG32 1457 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); RREG32 1458 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 1459 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); RREG32 1460 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); RREG32 1461 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); RREG32 1462 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); RREG32 1463 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); RREG32 1464 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); RREG32 1465 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); RREG32 1466 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); RREG32 1467 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); RREG32 1468 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); RREG32 1470 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmp = RREG32(RADEON_GPIO_MONID); RREG32 1499 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tmp = RREG32(RADEON_GPIO_MONID); RREG32 1586 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); RREG32 1589 drivers/gpu/drm/radeon/radeon_legacy_encoders.c gpiopad_a = RREG32(RADEON_GPIOPAD_A); RREG32 1590 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); RREG32 1592 drivers/gpu/drm/radeon/radeon_legacy_encoders.c disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); RREG32 1594 drivers/gpu/drm/radeon/radeon_legacy_encoders.c crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); RREG32 1596 drivers/gpu/drm/radeon/radeon_legacy_encoders.c tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); RREG32 1597 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); RREG32 1598 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dac_cntl2 = RREG32(RADEON_DAC_CNTL2); RREG32 1652 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) RREG32 1655 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) RREG32 285 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); RREG32 297 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); RREG32 315 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); RREG32 335 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); RREG32 341 drivers/gpu/drm/radeon/radeon_legacy_tv.c return RREG32(RADEON_TV_HOST_READ_DATA); RREG32 613 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = RREG32(RADEON_TV_VSCALER_CNTL1); RREG32 655 drivers/gpu/drm/radeon/radeon_legacy_tv.c tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; RREG32 754 drivers/gpu/drm/radeon/radeon_legacy_tv.c tmp = RREG32(RADEON_TV_DAC_CNTL); RREG32 303 drivers/gpu/drm/radeon/radeon_ring.c ptr = RREG32(ring->rptr_save_reg); RREG32 487 drivers/gpu/drm/radeon/radeon_ring.c rptr_next = RREG32(ring->rptr_save_reg); RREG32 982 drivers/gpu/drm/radeon/radeon_ttm.c value = RREG32(RADEON_MM_DATA); RREG32 1038 drivers/gpu/drm/radeon/radeon_uvd.c if ((RREG32(cg_upll_func_cntl) & mask) == mask) RREG32 158 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; RREG32 162 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; RREG32 249 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_MC_STATUS); RREG32 264 drivers/gpu/drm/radeon/rs400.c RREG32(RADEON_MC_STATUS)); RREG32 278 drivers/gpu/drm/radeon/rs400.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; RREG32 292 drivers/gpu/drm/radeon/rs400.c r = RREG32(RS480_NB_MC_DATA); RREG32 317 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_HOST_PATH_CNTL); RREG32 319 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_BUS_CNTL); RREG32 332 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RS690_HDP_FB_LOCATION); RREG32 335 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_AGP_BASE); RREG32 337 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RS480_AGP_BASE_2); RREG32 339 drivers/gpu/drm/radeon/rs400.c tmp = RREG32(RADEON_MC_AGP_LOCATION); RREG32 447 drivers/gpu/drm/radeon/rs400.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 477 drivers/gpu/drm/radeon/rs400.c RREG32(R_000E40_RBBM_STATUS), RREG32 478 drivers/gpu/drm/radeon/rs400.c RREG32(R_0007C0_CP_STAT)); RREG32 551 drivers/gpu/drm/radeon/rs400.c RREG32(R_000E40_RBBM_STATUS), RREG32 552 drivers/gpu/drm/radeon/rs400.c RREG32(R_0007C0_CP_STAT)); RREG32 63 drivers/gpu/drm/radeon/rs600.c if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) RREG32 73 drivers/gpu/drm/radeon/rs600.c pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 74 drivers/gpu/drm/radeon/rs600.c pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); RREG32 97 drivers/gpu/drm/radeon/rs600.c if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) RREG32 121 drivers/gpu/drm/radeon/rs600.c u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); RREG32 138 drivers/gpu/drm/radeon/rs600.c if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) RREG32 154 drivers/gpu/drm/radeon/rs600.c return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & RREG32 232 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(voltage->gpio.reg); RREG32 241 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(voltage->gpio.reg); RREG32 327 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); RREG32 345 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); RREG32 360 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); RREG32 365 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); RREG32 383 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); RREG32 391 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); RREG32 462 drivers/gpu/drm/radeon/rs600.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 468 drivers/gpu/drm/radeon/rs600.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 472 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(RADEON_CP_RB_CNTL); RREG32 484 drivers/gpu/drm/radeon/rs600.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 488 drivers/gpu/drm/radeon/rs600.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 492 drivers/gpu/drm/radeon/rs600.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 496 drivers/gpu/drm/radeon/rs600.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 500 drivers/gpu/drm/radeon/rs600.c RREG32(R_0000F0_RBBM_SOFT_RESET); RREG32 504 drivers/gpu/drm/radeon/rs600.c status = RREG32(R_000E40_RBBM_STATUS); RREG32 569 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; RREG32 664 drivers/gpu/drm/radeon/rs600.c u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & RREG32 666 drivers/gpu/drm/radeon/rs600.c u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & RREG32 670 drivers/gpu/drm/radeon/rs600.c hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & RREG32 708 drivers/gpu/drm/radeon/rs600.c RREG32(R_000040_GEN_INT_CNTL); RREG32 715 drivers/gpu/drm/radeon/rs600.c uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); RREG32 720 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); RREG32 730 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); RREG32 735 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); RREG32 744 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & RREG32 747 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); RREG32 762 drivers/gpu/drm/radeon/rs600.c u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & RREG32 833 drivers/gpu/drm/radeon/rs600.c msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; RREG32 848 drivers/gpu/drm/radeon/rs600.c return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); RREG32 850 drivers/gpu/drm/radeon/rs600.c return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); RREG32 881 drivers/gpu/drm/radeon/rs600.c rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); RREG32 913 drivers/gpu/drm/radeon/rs600.c d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); RREG32 914 drivers/gpu/drm/radeon/rs600.c d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); RREG32 932 drivers/gpu/drm/radeon/rs600.c r = RREG32(R_000074_MC_IND_DATA); RREG32 1019 drivers/gpu/drm/radeon/rs600.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 1053 drivers/gpu/drm/radeon/rs600.c RREG32(R_000E40_RBBM_STATUS), RREG32 1054 drivers/gpu/drm/radeon/rs600.c RREG32(R_0007C0_CP_STAT)); RREG32 1128 drivers/gpu/drm/radeon/rs600.c RREG32(R_000E40_RBBM_STATUS), RREG32 1129 drivers/gpu/drm/radeon/rs600.c RREG32(R_0007C0_CP_STAT)); RREG32 159 drivers/gpu/drm/radeon/rs690.c rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); RREG32 228 drivers/gpu/drm/radeon/rs690.c tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; RREG32 658 drivers/gpu/drm/radeon/rs690.c r = RREG32(R_00007C_MC_DATA); RREG32 730 drivers/gpu/drm/radeon/rs690.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 764 drivers/gpu/drm/radeon/rs690.c RREG32(R_000E40_RBBM_STATUS), RREG32 765 drivers/gpu/drm/radeon/rs690.c RREG32(R_0007C0_CP_STAT)); RREG32 840 drivers/gpu/drm/radeon/rs690.c RREG32(R_000E40_RBBM_STATUS), RREG32 841 drivers/gpu/drm/radeon/rs690.c RREG32(R_0007C0_CP_STAT)); RREG32 213 drivers/gpu/drm/radeon/rs780_dpm.c u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; RREG32 988 drivers/gpu/drm/radeon/rs780_dpm.c u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; RREG32 989 drivers/gpu/drm/radeon/rs780_dpm.c u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); RREG32 1010 drivers/gpu/drm/radeon/rs780_dpm.c u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; RREG32 1011 drivers/gpu/drm/radeon/rs780_dpm.c u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); RREG32 154 drivers/gpu/drm/radeon/rv515.c RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); RREG32 166 drivers/gpu/drm/radeon/rv515.c gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); RREG32 167 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(R300_DST_PIPE_CONFIG); RREG32 219 drivers/gpu/drm/radeon/rv515.c r = RREG32(MC_IND_DATA); RREG32 245 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(GB_PIPE_SELECT); RREG32 247 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(SU_REG_DEST); RREG32 249 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(GB_TILE_CONFIG); RREG32 251 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(DST_PIPE_CONFIG); RREG32 263 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(0x2140); RREG32 266 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(0x425C); RREG32 303 drivers/gpu/drm/radeon/rv515.c save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); RREG32 304 drivers/gpu/drm/radeon/rv515.c save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); RREG32 310 drivers/gpu/drm/radeon/rv515.c crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; RREG32 313 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); RREG32 331 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); RREG32 346 drivers/gpu/drm/radeon/rv515.c blackout = RREG32(R700_MC_CITF_CNTL); RREG32 348 drivers/gpu/drm/radeon/rv515.c blackout = RREG32(R600_CITF_CNTL); RREG32 366 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); RREG32 371 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); RREG32 410 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); RREG32 416 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); RREG32 421 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); RREG32 427 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); RREG32 438 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(R700_MC_CITF_CNTL); RREG32 440 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(R600_CITF_CNTL); RREG32 452 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); RREG32 553 drivers/gpu/drm/radeon/rv515.c rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); RREG32 582 drivers/gpu/drm/radeon/rv515.c RREG32(R_000E40_RBBM_STATUS), RREG32 583 drivers/gpu/drm/radeon/rv515.c RREG32(R_0007C0_CP_STAT)); RREG32 662 drivers/gpu/drm/radeon/rv515.c RREG32(R_000E40_RBBM_STATUS), RREG32 663 drivers/gpu/drm/radeon/rv515.c RREG32(R_0007C0_CP_STAT)); RREG32 787 drivers/gpu/drm/radeon/rv6xx_dpm.c tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; RREG32 789 drivers/gpu/drm/radeon/rv6xx_dpm.c dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3); RREG32 1182 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 2035 drivers/gpu/drm/radeon/rv6xx_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2060 drivers/gpu/drm/radeon/rv6xx_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2083 drivers/gpu/drm/radeon/rv6xx_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 202 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_FUNC_CNTL); RREG32 204 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 206 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 208 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 210 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 213 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(TCI_MCLK_PWRMGT_CNTL); RREG32 215 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(TCI_DLL_CNTL); RREG32 217 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_MPLL_FUNC_CNTL); RREG32 219 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_MPLL_FUNC_CNTL_2); RREG32 221 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_MPLL_FUNC_CNTL_3); RREG32 223 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM); RREG32 225 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2); RREG32 402 drivers/gpu/drm/radeon/rv730_dpm.c arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) & RREG32 411 drivers/gpu/drm/radeon/rv730_dpm.c old_dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 412 drivers/gpu/drm/radeon/rv730_dpm.c old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 418 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 419 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 428 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 429 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 438 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 439 drivers/gpu/drm/radeon/rv730_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 481 drivers/gpu/drm/radeon/rv730_dpm.c mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); RREG32 487 drivers/gpu/drm/radeon/rv730_dpm.c mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); RREG32 502 drivers/gpu/drm/radeon/rv730_dpm.c mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); RREG32 505 drivers/gpu/drm/radeon/rv730_dpm.c mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); RREG32 289 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_FUNC_CNTL); RREG32 291 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 293 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 295 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 297 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 300 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(MPLL_AD_FUNC_CNTL); RREG32 302 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(MPLL_AD_FUNC_CNTL_2); RREG32 304 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(MPLL_DQ_FUNC_CNTL); RREG32 306 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(MPLL_DQ_FUNC_CNTL_2); RREG32 308 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(MCLK_PWRMGT_CNTL); RREG32 309 drivers/gpu/drm/radeon/rv740_dpm.c pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL); RREG32 310 drivers/gpu/drm/radeon/rv740_dpm.c pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1); RREG32 311 drivers/gpu/drm/radeon/rv740_dpm.c pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2); RREG32 797 drivers/gpu/drm/radeon/rv770.c u32 tmp = RREG32(CG_CLKPIN_CNTL); RREG32 811 drivers/gpu/drm/radeon/rv770.c u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); RREG32 835 drivers/gpu/drm/radeon/rv770.c if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) RREG32 851 drivers/gpu/drm/radeon/rv770.c return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & RREG32 858 drivers/gpu/drm/radeon/rv770.c u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> RREG32 1025 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(HDP_DEBUG1); RREG32 1109 drivers/gpu/drm/radeon/rv770.c RREG32(GRBM_SOFT_RESET); RREG32 1145 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 1151 drivers/gpu/drm/radeon/rv770.c if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS) RREG32 1159 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(MPLL_CNTL_MODE); RREG32 1303 drivers/gpu/drm/radeon/rv770.c mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); RREG32 1305 drivers/gpu/drm/radeon/rv770.c shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); RREG32 1319 drivers/gpu/drm/radeon/rv770.c cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; RREG32 1341 drivers/gpu/drm/radeon/rv770.c disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; RREG32 1406 drivers/gpu/drm/radeon/rv770.c ta_aux_cntl = RREG32(TA_CNTL_AUX); RREG32 1409 drivers/gpu/drm/radeon/rv770.c sx_debug_1 = RREG32(SX_DEBUG_1); RREG32 1413 drivers/gpu/drm/radeon/rv770.c smx_dc_ctl0 = RREG32(SMX_DC_CTL0); RREG32 1427 drivers/gpu/drm/radeon/rv770.c db_debug3 = RREG32(DB_DEBUG3); RREG32 1443 drivers/gpu/drm/radeon/rv770.c db_debug4 = RREG32(DB_DEBUG4); RREG32 1483 drivers/gpu/drm/radeon/rv770.c sq_config = RREG32(SQ_CONFIG); RREG32 1596 drivers/gpu/drm/radeon/rv770.c hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); RREG32 1652 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 1660 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(MC_SHARED_CHMAP); RREG32 1681 drivers/gpu/drm/radeon/rv770.c rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 1682 drivers/gpu/drm/radeon/rv770.c rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); RREG32 2070 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(0x541c); RREG32 138 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(GB_TILING_CONFIG); RREG32 170 drivers/gpu/drm/radeon/rv770_dpm.c if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) RREG32 172 drivers/gpu/drm/radeon/rv770_dpm.c if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) RREG32 206 drivers/gpu/drm/radeon/rv770_dpm.c if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN) RREG32 729 drivers/gpu/drm/radeon/rv770_dpm.c tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; RREG32 731 drivers/gpu/drm/radeon/rv770_dpm.c tmp = RREG32(MC_SEQ_MISC0) & 3; RREG32 879 drivers/gpu/drm/radeon/rv770_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 1305 drivers/gpu/drm/radeon/rv770_dpm.c return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); RREG32 1343 drivers/gpu/drm/radeon/rv770_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 1521 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_FUNC_CNTL); RREG32 1523 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 1525 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 1527 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 1529 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 1531 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(MPLL_AD_FUNC_CNTL); RREG32 1533 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(MPLL_AD_FUNC_CNTL_2); RREG32 1535 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(MPLL_DQ_FUNC_CNTL); RREG32 1537 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(MPLL_DQ_FUNC_CNTL_2); RREG32 1539 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(MCLK_PWRMGT_CNTL); RREG32 1540 drivers/gpu/drm/radeon/rv770_dpm.c pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL); RREG32 1558 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(S0_VID_LOWER_SMIO_CNTL); RREG32 1567 drivers/gpu/drm/radeon/rv770_dpm.c (RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT; RREG32 1570 drivers/gpu/drm/radeon/rv770_dpm.c vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL); RREG32 1573 drivers/gpu/drm/radeon/rv770_dpm.c vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL); RREG32 1576 drivers/gpu/drm/radeon/rv770_dpm.c vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL); RREG32 1594 drivers/gpu/drm/radeon/rv770_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 1635 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(GB_TILING_CONFIG); RREG32 1657 drivers/gpu/drm/radeon/rv770_dpm.c if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1) RREG32 2472 drivers/gpu/drm/radeon/rv770_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2501 drivers/gpu/drm/radeon/rv770_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 2523 drivers/gpu/drm/radeon/rv770_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> RREG32 335 drivers/gpu/drm/radeon/rv770_smc.c original_data = RREG32(SMC_SRAM_DATA); RREG32 416 drivers/gpu/drm/radeon/rv770_smc.c tmp = RREG32(SMC_IO); RREG32 436 drivers/gpu/drm/radeon/rv770_smc.c tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; RREG32 443 drivers/gpu/drm/radeon/rv770_smc.c tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; RREG32 459 drivers/gpu/drm/radeon/rv770_smc.c if (RREG32(SMC_IO) & SMC_STOP_MODE) RREG32 612 drivers/gpu/drm/radeon/rv770_smc.c *value = RREG32(SMC_SRAM_DATA); RREG32 1325 drivers/gpu/drm/radeon/si.c *val = RREG32(reg); RREG32 1348 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_CLKPIN_CNTL_2); RREG32 1352 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_CLKPIN_CNTL); RREG32 1365 drivers/gpu/drm/radeon/si.c temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> RREG32 1628 drivers/gpu/drm/radeon/si.c running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; RREG32 1660 drivers/gpu/drm/radeon/si.c if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) RREG32 1665 drivers/gpu/drm/radeon/si.c if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) RREG32 1780 drivers/gpu/drm/radeon/si.c if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) RREG32 2010 drivers/gpu/drm/radeon/si.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & RREG32 2032 drivers/gpu/drm/radeon/si.c u32 tmp = RREG32(MC_SHARED_CHMAP); RREG32 2435 drivers/gpu/drm/radeon/si.c arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); RREG32 2444 drivers/gpu/drm/radeon/si.c tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); RREG32 2982 drivers/gpu/drm/radeon/si.c data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); RREG32 2987 drivers/gpu/drm/radeon/si.c data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); RREG32 3006 drivers/gpu/drm/radeon/si.c data = RREG32(SPI_STATIC_THREAD_MGMT_3); RREG32 3029 drivers/gpu/drm/radeon/si.c data = RREG32(CC_RB_BACKEND_DISABLE); RREG32 3034 drivers/gpu/drm/radeon/si.c data |= RREG32(GC_USER_RB_BACKEND_DISABLE); RREG32 3208 drivers/gpu/drm/radeon/si.c mc_shared_chmap = RREG32(MC_SHARED_CHMAP); RREG32 3209 drivers/gpu/drm/radeon/si.c mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); RREG32 3313 drivers/gpu/drm/radeon/si.c sx_debug_1 = RREG32(SX_DEBUG_1); RREG32 3347 drivers/gpu/drm/radeon/si.c tmp = RREG32(HDP_MISC_CNTL); RREG32 3351 drivers/gpu/drm/radeon/si.c hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); RREG32 3780 drivers/gpu/drm/radeon/si.c tmp = RREG32(GRBM_STATUS); RREG32 3797 drivers/gpu/drm/radeon/si.c tmp = RREG32(GRBM_STATUS2); RREG32 3802 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); RREG32 3807 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); RREG32 3812 drivers/gpu/drm/radeon/si.c tmp = RREG32(SRBM_STATUS2); RREG32 3820 drivers/gpu/drm/radeon/si.c tmp = RREG32(SRBM_STATUS); RREG32 3842 drivers/gpu/drm/radeon/si.c tmp = RREG32(VM_L2_STATUS); RREG32 3868 drivers/gpu/drm/radeon/si.c RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); RREG32 3870 drivers/gpu/drm/radeon/si.c RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); RREG32 3884 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); RREG32 3890 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); RREG32 3951 drivers/gpu/drm/radeon/si.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3955 drivers/gpu/drm/radeon/si.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3961 drivers/gpu/drm/radeon/si.c tmp = RREG32(GRBM_SOFT_RESET); RREG32 3965 drivers/gpu/drm/radeon/si.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 3969 drivers/gpu/drm/radeon/si.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 3975 drivers/gpu/drm/radeon/si.c tmp = RREG32(SRBM_SOFT_RESET); RREG32 3991 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); RREG32 3995 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 4000 drivers/gpu/drm/radeon/si.c if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS) RREG32 4005 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 4009 drivers/gpu/drm/radeon/si.c tmp = RREG32(MPLL_CNTL_MODE); RREG32 4018 drivers/gpu/drm/radeon/si.c tmp = RREG32(SPLL_CNTL_MODE); RREG32 4022 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); RREG32 4026 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); RREG32 4030 drivers/gpu/drm/radeon/si.c tmp = RREG32(SPLL_CNTL_MODE); RREG32 4051 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); RREG32 4055 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); RREG32 4081 drivers/gpu/drm/radeon/si.c if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) RREG32 4213 drivers/gpu/drm/radeon/si.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 4221 drivers/gpu/drm/radeon/si.c tmp = RREG32(MC_SHARED_CHMAP); RREG32 4257 drivers/gpu/drm/radeon/si.c tmp = RREG32(CONFIG_MEMSIZE); RREG32 4383 drivers/gpu/drm/radeon/si.c rdev->vm_manager.saved_table_addr[i] = RREG32(reg); RREG32 5133 drivers/gpu/drm/radeon/si.c if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) RREG32 5139 drivers/gpu/drm/radeon/si.c if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) RREG32 5148 drivers/gpu/drm/radeon/si.c u32 tmp = RREG32(CP_INT_CNTL_RING0); RREG32 5160 drivers/gpu/drm/radeon/si.c tmp = RREG32(DB_DEPTH_INFO); RREG32 5164 drivers/gpu/drm/radeon/si.c if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) RREG32 5176 drivers/gpu/drm/radeon/si.c tmp = RREG32(UVD_CGC_CTRL); RREG32 5199 drivers/gpu/drm/radeon/si.c u32 tmp = RREG32(UVD_CGC_CTRL); RREG32 5209 drivers/gpu/drm/radeon/si.c orig = data = RREG32(RLC_CNTL); RREG32 5225 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_CNTL); RREG32 5234 drivers/gpu/drm/radeon/si.c orig = data = RREG32(DMA_PG); RREG32 5263 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_PG_CNTL); RREG32 5267 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RREG32 5271 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RREG32 5275 drivers/gpu/drm/radeon/si.c tmp = RREG32(DB_RENDER_CONTROL); RREG32 5285 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_PG_CNTL); RREG32 5291 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RREG32 5305 drivers/gpu/drm/radeon/si.c tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); RREG32 5306 drivers/gpu/drm/radeon/si.c tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); RREG32 5349 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_MAX_PG_CU); RREG32 5360 drivers/gpu/drm/radeon/si.c orig = data = RREG32(RLC_CGCG_CGLS_CTRL); RREG32 5383 drivers/gpu/drm/radeon/si.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 5384 drivers/gpu/drm/radeon/si.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 5385 drivers/gpu/drm/radeon/si.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 5386 drivers/gpu/drm/radeon/si.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 5401 drivers/gpu/drm/radeon/si.c orig = data = RREG32(CGTS_SM_CTRL_REG); RREG32 5407 drivers/gpu/drm/radeon/si.c orig = data = RREG32(CP_MEM_SLP_CNTL); RREG32 5413 drivers/gpu/drm/radeon/si.c orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); RREG32 5426 drivers/gpu/drm/radeon/si.c orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); RREG32 5431 drivers/gpu/drm/radeon/si.c data = RREG32(CP_MEM_SLP_CNTL); RREG32 5436 drivers/gpu/drm/radeon/si.c orig = data = RREG32(CGTS_SM_CTRL_REG); RREG32 5461 drivers/gpu/drm/radeon/si.c orig = data = RREG32(UVD_CGC_CTRL); RREG32 5473 drivers/gpu/drm/radeon/si.c orig = data = RREG32(UVD_CGC_CTRL); RREG32 5503 drivers/gpu/drm/radeon/si.c orig = data = RREG32(mc_cg_registers[i]); RREG32 5520 drivers/gpu/drm/radeon/si.c orig = data = RREG32(mc_cg_registers[i]); RREG32 5542 drivers/gpu/drm/radeon/si.c orig = data = RREG32(DMA_POWER_CNTL + offset); RREG32 5554 drivers/gpu/drm/radeon/si.c orig = data = RREG32(DMA_POWER_CNTL + offset); RREG32 5559 drivers/gpu/drm/radeon/si.c orig = data = RREG32(DMA_CLK_CTRL + offset); RREG32 5590 drivers/gpu/drm/radeon/si.c orig = data = RREG32(HDP_HOST_PATH_CNTL); RREG32 5606 drivers/gpu/drm/radeon/si.c orig = data = RREG32(HDP_MEM_POWER_LS); RREG32 5809 drivers/gpu/drm/radeon/si.c u32 tmp = RREG32(GRBM_SOFT_RESET); RREG32 5842 drivers/gpu/drm/radeon/si.c tmp = RREG32(MC_SEQ_MISC0); RREG32 5852 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_LB_CNTL); RREG32 5922 drivers/gpu/drm/radeon/si.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 5923 drivers/gpu/drm/radeon/si.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 5934 drivers/gpu/drm/radeon/si.c u32 ih_rb_cntl = RREG32(IH_RB_CNTL); RREG32 5935 drivers/gpu/drm/radeon/si.c u32 ih_cntl = RREG32(IH_CNTL); RREG32 5953 drivers/gpu/drm/radeon/si.c tmp = RREG32(CP_INT_CNTL_RING0) & RREG32 5958 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 5960 drivers/gpu/drm/radeon/si.c tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 6002 drivers/gpu/drm/radeon/si.c interrupt_cntl = RREG32(INTERRUPT_CNTL); RREG32 6071 drivers/gpu/drm/radeon/si.c cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & RREG32 6074 drivers/gpu/drm/radeon/si.c dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 6075 drivers/gpu/drm/radeon/si.c dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; RREG32 6077 drivers/gpu/drm/radeon/si.c thermal_int = RREG32(CG_THERMAL_INT) & RREG32 6139 drivers/gpu/drm/radeon/si.c RREG32(SRBM_STATUS); RREG32 6155 drivers/gpu/drm/radeon/si.c disp_int[i] = RREG32(si_disp_int_status[i]); RREG32 6157 drivers/gpu/drm/radeon/si.c grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); RREG32 6217 drivers/gpu/drm/radeon/si.c wptr = RREG32(IH_RB_WPTR); RREG32 6228 drivers/gpu/drm/radeon/si.c tmp = RREG32(IH_RB_CNTL); RREG32 6363 drivers/gpu/drm/radeon/si.c DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); RREG32 6372 drivers/gpu/drm/radeon/si.c addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); RREG32 6373 drivers/gpu/drm/radeon/si.c status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); RREG32 6991 drivers/gpu/drm/radeon/si.c clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | RREG32 6992 drivers/gpu/drm/radeon/si.c ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); RREG32 7395 drivers/gpu/drm/radeon/si.c orig = data = RREG32(THM_CLK_CNTL); RREG32 7401 drivers/gpu/drm/radeon/si.c orig = data = RREG32(MISC_CLK_CNTL); RREG32 7407 drivers/gpu/drm/radeon/si.c orig = data = RREG32(CG_CLKPIN_CNTL); RREG32 7412 drivers/gpu/drm/radeon/si.c orig = data = RREG32(CG_CLKPIN_CNTL_2); RREG32 7417 drivers/gpu/drm/radeon/si.c orig = data = RREG32(MPLL_BYPASSCLK_SEL); RREG32 7423 drivers/gpu/drm/radeon/si.c orig = data = RREG32(SPLL_CNTL_MODE); RREG32 2111 drivers/gpu/drm/radeon/si_dpm.c cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; RREG32 2672 drivers/gpu/drm/radeon/si_dpm.c reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; RREG32 2755 drivers/gpu/drm/radeon/si_dpm.c data = RREG32(config_regs->offset << 2); RREG32 3211 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(MC_SEQ_MISC0); RREG32 3217 drivers/gpu/drm/radeon/si_dpm.c width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; RREG32 3219 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(MC_ARB_RAMCFG); RREG32 3572 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); RREG32 3573 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); RREG32 3574 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); RREG32 3575 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); RREG32 3576 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); RREG32 3577 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); RREG32 3578 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); RREG32 3579 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); RREG32 3580 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); RREG32 3581 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); RREG32 3582 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); RREG32 3583 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); RREG32 3584 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); RREG32 3585 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); RREG32 3586 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); RREG32 3622 drivers/gpu/drm/radeon/si_dpm.c if (RREG32(SMC_RESP_0) == 1) RREG32 3687 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); RREG32 3700 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); RREG32 3801 drivers/gpu/drm/radeon/si_dpm.c u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); RREG32 4280 drivers/gpu/drm/radeon/si_dpm.c u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; RREG32 4287 drivers/gpu/drm/radeon/si_dpm.c dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); RREG32 4308 drivers/gpu/drm/radeon/si_dpm.c dram_timing = RREG32(MC_ARB_DRAM_TIMING); RREG32 4309 drivers/gpu/drm/radeon/si_dpm.c dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); RREG32 4310 drivers/gpu/drm/radeon/si_dpm.c burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; RREG32 5004 drivers/gpu/drm/radeon/si_dpm.c (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && RREG32 5023 drivers/gpu/drm/radeon/si_dpm.c ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) RREG32 5024 drivers/gpu/drm/radeon/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 5026 drivers/gpu/drm/radeon/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; RREG32 5034 drivers/gpu/drm/radeon/si_dpm.c dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; RREG32 5368 drivers/gpu/drm/radeon/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_EMRS); RREG32 5379 drivers/gpu/drm/radeon/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS); RREG32 5405 drivers/gpu/drm/radeon/si_dpm.c temp_reg = RREG32(MC_PMG_CMD_MRS1); RREG32 5545 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); RREG32 5546 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); RREG32 5547 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); RREG32 5548 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); RREG32 5549 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); RREG32 5550 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); RREG32 5551 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); RREG32 5552 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); RREG32 5553 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); RREG32 5554 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); RREG32 5555 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); RREG32 5556 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); RREG32 5557 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); RREG32 5558 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); RREG32 5961 drivers/gpu/drm/radeon/si_dpm.c u32 thermal_int = RREG32(CG_THERMAL_INT); RREG32 6014 drivers/gpu/drm/radeon/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; RREG32 6016 drivers/gpu/drm/radeon/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; RREG32 6021 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32 6025 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32 6046 drivers/gpu/drm/radeon/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6090 drivers/gpu/drm/radeon/si_dpm.c tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; RREG32 6145 drivers/gpu/drm/radeon/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6146 drivers/gpu/drm/radeon/si_dpm.c duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; RREG32 6178 drivers/gpu/drm/radeon/si_dpm.c duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; RREG32 6187 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; RREG32 6218 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; RREG32 6235 drivers/gpu/drm/radeon/si_dpm.c tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; RREG32 6264 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; RREG32 6280 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; RREG32 6284 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; RREG32 6304 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; RREG32 6309 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; RREG32 7100 drivers/gpu/drm/radeon/si_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 7120 drivers/gpu/drm/radeon/si_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 7138 drivers/gpu/drm/radeon/si_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> RREG32 86 drivers/gpu/drm/radeon/si_smc.c original_data = RREG32(SMC_IND_DATA_0); RREG32 126 drivers/gpu/drm/radeon/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 127 drivers/gpu/drm/radeon/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 128 drivers/gpu/drm/radeon/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 129 drivers/gpu/drm/radeon/si_smc.c RREG32(CB_CGTT_SCLK_CTRL); RREG32 183 drivers/gpu/drm/radeon/si_smc.c tmp = RREG32(SMC_RESP_0); RREG32 188 drivers/gpu/drm/radeon/si_smc.c tmp = RREG32(SMC_RESP_0); RREG32 291 drivers/gpu/drm/radeon/si_smc.c *value = RREG32(SMC_IND_DATA_0); RREG32 96 drivers/gpu/drm/radeon/sumo_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 108 drivers/gpu/drm/radeon/sumo_dpm.c local0 = RREG32(CG_CGTT_LOCAL_0); RREG32 109 drivers/gpu/drm/radeon/sumo_dpm.c local1 = RREG32(CG_CGTT_LOCAL_1); RREG32 280 drivers/gpu/drm/radeon/sumo_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 499 drivers/gpu/drm/radeon/sumo_dpm.c u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); RREG32 513 drivers/gpu/drm/radeon/sumo_dpm.c u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); RREG32 523 drivers/gpu/drm/radeon/sumo_dpm.c u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL); RREG32 539 drivers/gpu/drm/radeon/sumo_dpm.c cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); RREG32 552 drivers/gpu/drm/radeon/sumo_dpm.c u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS; RREG32 601 drivers/gpu/drm/radeon/sumo_dpm.c if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE) RREG32 631 drivers/gpu/drm/radeon/sumo_dpm.c if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT) RREG32 642 drivers/gpu/drm/radeon/sumo_dpm.c if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0) RREG32 647 drivers/gpu/drm/radeon/sumo_dpm.c if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0) RREG32 740 drivers/gpu/drm/radeon/sumo_dpm.c u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); RREG32 802 drivers/gpu/drm/radeon/sumo_dpm.c u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4); RREG32 877 drivers/gpu/drm/radeon/sumo_dpm.c u32 v = RREG32(DOUT_SCRATCH3); RREG32 891 drivers/gpu/drm/radeon/sumo_dpm.c u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL); RREG32 892 drivers/gpu/drm/radeon/sumo_dpm.c u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2); RREG32 929 drivers/gpu/drm/radeon/sumo_dpm.c u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); RREG32 942 drivers/gpu/drm/radeon/sumo_dpm.c u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); RREG32 971 drivers/gpu/drm/radeon/sumo_dpm.c u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); RREG32 1743 drivers/gpu/drm/radeon/sumo_dpm.c u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; RREG32 1820 drivers/gpu/drm/radeon/sumo_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >> RREG32 1847 drivers/gpu/drm/radeon/sumo_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >> RREG32 41 drivers/gpu/drm/radeon/sumo_smc.c if (RREG32(GFX_INT_STATUS) & INT_DONE) RREG32 50 drivers/gpu/drm/radeon/sumo_smc.c if (RREG32(GFX_INT_REQ) & INT_REQ) RREG32 56 drivers/gpu/drm/radeon/sumo_smc.c if (RREG32(GFX_INT_STATUS) & INT_ACK) RREG32 62 drivers/gpu/drm/radeon/sumo_smc.c if (RREG32(GFX_INT_STATUS) & INT_DONE) RREG32 372 drivers/gpu/drm/radeon/trinity_dpm.c u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; RREG32 452 drivers/gpu/drm/radeon/trinity_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 513 drivers/gpu/drm/radeon/trinity_dpm.c RREG32(GB_ADDR_CONFIG); RREG32 774 drivers/gpu/drm/radeon/trinity_dpm.c if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) RREG32 779 drivers/gpu/drm/radeon/trinity_dpm.c if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0) RREG32 784 drivers/gpu/drm/radeon/trinity_dpm.c if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) RREG32 819 drivers/gpu/drm/radeon/trinity_dpm.c if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) RREG32 940 drivers/gpu/drm/radeon/trinity_dpm.c u32 tmp = RREG32(CG_MISC_REG); RREG32 2038 drivers/gpu/drm/radeon/trinity_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >> RREG32 2059 drivers/gpu/drm/radeon/trinity_dpm.c (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >> RREG32 36 drivers/gpu/drm/radeon/trinity_smc.c if (RREG32(SMC_RESP_0) != 0) RREG32 40 drivers/gpu/drm/radeon/trinity_smc.c v = RREG32(SMC_RESP_0); RREG32 117 drivers/gpu/drm/radeon/trinity_smc.c if ((RREG32(SMC_INT_REQ) & 0xffff) == 1) RREG32 42 drivers/gpu/drm/radeon/uvd_v1_0.c return RREG32(UVD_RBC_RB_RPTR); RREG32 56 drivers/gpu/drm/radeon/uvd_v1_0.c return RREG32(UVD_RBC_RB_WPTR); RREG32 332 drivers/gpu/drm/radeon/uvd_v1_0.c status = RREG32(UVD_STATUS); RREG32 370 drivers/gpu/drm/radeon/uvd_v1_0.c ring->wptr = RREG32(UVD_RBC_RB_RPTR); RREG32 438 drivers/gpu/drm/radeon/uvd_v1_0.c tmp = RREG32(UVD_CONTEXT_ID); RREG32 63 drivers/gpu/drm/radeon/vce_v1_0.c return RREG32(VCE_RB_RPTR); RREG32 65 drivers/gpu/drm/radeon/vce_v1_0.c return RREG32(VCE_RB_RPTR2); RREG32 80 drivers/gpu/drm/radeon/vce_v1_0.c return RREG32(VCE_RB_WPTR); RREG32 82 drivers/gpu/drm/radeon/vce_v1_0.c return RREG32(VCE_RB_WPTR2); RREG32 107 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_CLOCK_GATING_A); RREG32 111 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 116 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 120 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_CLOCK_GATING_A); RREG32 124 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 129 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 139 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_CLOCK_GATING_A); RREG32 143 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_CLOCK_GATING_B); RREG32 148 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 152 drivers/gpu/drm/radeon/vce_v1_0.c tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 258 drivers/gpu/drm/radeon/vce_v1_0.c if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE) RREG32 265 drivers/gpu/drm/radeon/vce_v1_0.c if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS)) RREG32 270 drivers/gpu/drm/radeon/vce_v1_0.c if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY)) RREG32 328 drivers/gpu/drm/radeon/vce_v1_0.c status = RREG32(VCE_STATUS); RREG32 43 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_CLOCK_GATING_B); RREG32 47 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 51 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 57 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_CLOCK_GATING_B); RREG32 62 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 67 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 77 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_CLOCK_GATING_B); RREG32 87 drivers/gpu/drm/radeon/vce_v2_0.c orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 93 drivers/gpu/drm/radeon/vce_v2_0.c orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); RREG32 134 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_CLOCK_GATING_A); RREG32 140 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_UENC_CLOCK_GATING); RREG32 145 drivers/gpu/drm/radeon/vce_v2_0.c tmp = RREG32(VCE_CLOCK_GATING_B); RREG32 507 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); RREG32 550 drivers/misc/habanalabs/goya/goya.c RREG32(mmDMA_QM_0_GLBL_PROT); RREG32 563 drivers/misc/habanalabs/goya/goya.c prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR); RREG32 564 drivers/misc/habanalabs/goya/goya.c prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF); RREG32 565 drivers/misc/habanalabs/goya/goya.c prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD); RREG32 566 drivers/misc/habanalabs/goya/goya.c prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); RREG32 894 drivers/misc/habanalabs/goya/goya.c status = RREG32(cp_sts_reg); RREG32 1123 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset); RREG32 1169 drivers/misc/habanalabs/goya/goya.c val = RREG32(tpc_slm_offset); RREG32 2224 drivers/misc/habanalabs/goya/goya.c RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); RREG32 2227 drivers/misc/habanalabs/goya/goya.c unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); RREG32 2229 drivers/misc/habanalabs/goya/goya.c RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); RREG32 2231 drivers/misc/habanalabs/goya/goya.c RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); RREG32 2252 drivers/misc/habanalabs/goya/goya.c RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); RREG32 2270 drivers/misc/habanalabs/goya/goya.c ver_off = RREG32(mmUBOOT_VER_OFFSET); RREG32 2275 drivers/misc/habanalabs/goya/goya.c ver_off = RREG32(mmPREBOOT_VER_OFFSET); RREG32 2525 drivers/misc/habanalabs/goya/goya.c RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); RREG32 2577 drivers/misc/habanalabs/goya/goya.c RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); RREG32 2628 drivers/misc/habanalabs/goya/goya.c status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); RREG32 4040 drivers/misc/habanalabs/goya/goya.c i = RREG32(mmSYNC_MNGR_SOB_OBJ_0); RREG32 4065 drivers/misc/habanalabs/goya/goya.c *val = RREG32(addr - CFG_BASE); RREG32 4366 drivers/misc/habanalabs/goya/goya.c if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) { RREG32 4371 drivers/misc/habanalabs/goya/goya.c if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) { RREG32 4376 drivers/misc/habanalabs/goya/goya.c if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) { RREG32 4381 drivers/misc/habanalabs/goya/goya.c if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) { RREG32 4396 drivers/misc/habanalabs/goya/goya.c val = RREG32(mmMMU_PAGE_ERROR_CAPTURE); RREG32 4400 drivers/misc/habanalabs/goya/goya.c addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA); RREG32 4794 drivers/misc/habanalabs/goya/goya.c RREG32(mmCPU_IF_AWUSER_OVR_EN); RREG32 4944 drivers/misc/habanalabs/goya/goya.c inv_data = RREG32(mmSTLB_CACHE_INV); RREG32 5028 drivers/misc/habanalabs/goya/goya.c qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset); RREG32 5029 drivers/misc/habanalabs/goya/goya.c dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset); RREG32 5049 drivers/misc/habanalabs/goya/goya.c qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset); RREG32 5050 drivers/misc/habanalabs/goya/goya.c cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset); RREG32 5051 drivers/misc/habanalabs/goya/goya.c tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset); RREG32 5069 drivers/misc/habanalabs/goya/goya.c qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0); RREG32 5070 drivers/misc/habanalabs/goya/goya.c cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0); RREG32 5071 drivers/misc/habanalabs/goya/goya.c mme_arch_sts = RREG32(mmMME_ARCH_STATUS); RREG32 5120 drivers/misc/habanalabs/goya/goya.c return RREG32(mmHW_STATE); RREG32 315 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(base_reg + 0x304); RREG32 386 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(base_reg + 0x304); RREG32 454 drivers/misc/habanalabs/goya/goya_coresight.c rwp = RREG32(base_reg + 0x18); RREG32 455 drivers/misc/habanalabs/goya/goya_coresight.c rwphi = RREG32(base_reg + 0x3c) & 0xff; RREG32 625 drivers/misc/habanalabs/goya/goya_coresight.c output[i] = RREG32(base_reg + i * 8); RREG32 627 drivers/misc/habanalabs/goya/goya_coresight.c output[overflow_idx] = RREG32(base_reg + 0xCC0); RREG32 629 drivers/misc/habanalabs/goya/goya_coresight.c output[cycle_cnt_idx] = RREG32(base_reg + 0xFC); RREG32 631 drivers/misc/habanalabs/goya/goya_coresight.c output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8); RREG32 674 drivers/misc/habanalabs/goya/goya_coresight.c val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); RREG32 1041 drivers/misc/habanalabs/habanalabs.h u32 tmp_ = RREG32(reg); \ RREG32 1052 drivers/misc/habanalabs/habanalabs.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \ RREG32 1069 drivers/misc/habanalabs/habanalabs.h (val) = RREG32(addr); \ RREG32 1073 drivers/misc/habanalabs/habanalabs.h (val) = RREG32(addr); \