RR 132 arch/powerpc/xmon/spu-insns.h APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ RR 133 arch/powerpc/xmon/spu-insns.h APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ RR 134 arch/powerpc/xmon/spu-insns.h APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ RR 135 arch/powerpc/xmon/spu-insns.h APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ RR 136 arch/powerpc/xmon/spu-insns.h APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ RR 137 arch/powerpc/xmon/spu-insns.h APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ RR 138 arch/powerpc/xmon/spu-insns.h APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ RR 139 arch/powerpc/xmon/spu-insns.h APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ RR 140 arch/powerpc/xmon/spu-insns.h APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ RR 149 arch/powerpc/xmon/spu-insns.h APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ RR 150 arch/powerpc/xmon/spu-insns.h APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ RR 152 arch/powerpc/xmon/spu-insns.h APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ RR 153 arch/powerpc/xmon/spu-insns.h APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ RR 154 arch/powerpc/xmon/spu-insns.h APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ RR 155 arch/powerpc/xmon/spu-insns.h APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ RR 156 arch/powerpc/xmon/spu-insns.h APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ RR 158 arch/powerpc/xmon/spu-insns.h APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ RR 159 arch/powerpc/xmon/spu-insns.h APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ RR 160 arch/powerpc/xmon/spu-insns.h APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ RR 161 arch/powerpc/xmon/spu-insns.h APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ RR 162 arch/powerpc/xmon/spu-insns.h APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ RR 163 arch/powerpc/xmon/spu-insns.h APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ RR 164 arch/powerpc/xmon/spu-insns.h APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ RR 165 arch/powerpc/xmon/spu-insns.h APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ RR 177 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ RR 178 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 179 arch/powerpc/xmon/spu-insns.h APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ RR 180 arch/powerpc/xmon/spu-insns.h APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 181 arch/powerpc/xmon/spu-insns.h APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ RR 182 arch/powerpc/xmon/spu-insns.h APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ RR 183 arch/powerpc/xmon/spu-insns.h APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ RR 184 arch/powerpc/xmon/spu-insns.h APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ RR 185 arch/powerpc/xmon/spu-insns.h APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */ RR 186 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */ RR 187 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */ RR 188 arch/powerpc/xmon/spu-insns.h APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */ RR 189 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */ RR 190 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */ RR 191 arch/powerpc/xmon/spu-insns.h APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */ RR 192 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */ RR 193 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */ RR 194 arch/powerpc/xmon/spu-insns.h APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */ RR 195 arch/powerpc/xmon/spu-insns.h APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */ RR 201 arch/powerpc/xmon/spu-insns.h APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */ RR 202 arch/powerpc/xmon/spu-insns.h APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */ RR 210 arch/powerpc/xmon/spu-insns.h APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ RR 239 arch/powerpc/xmon/spu-insns.h APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ RR 240 arch/powerpc/xmon/spu-insns.h APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ RR 241 arch/powerpc/xmon/spu-insns.h APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ RR 242 arch/powerpc/xmon/spu-insns.h APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ RR 243 arch/powerpc/xmon/spu-insns.h APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ RR 244 arch/powerpc/xmon/spu-insns.h APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ RR 245 arch/powerpc/xmon/spu-insns.h APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ RR 246 arch/powerpc/xmon/spu-insns.h APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ RR 247 arch/powerpc/xmon/spu-insns.h APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ RR 248 arch/powerpc/xmon/spu-insns.h APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ RR 257 arch/powerpc/xmon/spu-insns.h APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ RR 258 arch/powerpc/xmon/spu-insns.h APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ RR 259 arch/powerpc/xmon/spu-insns.h APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ RR 260 arch/powerpc/xmon/spu-insns.h APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ RR 261 arch/powerpc/xmon/spu-insns.h APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ RR 262 arch/powerpc/xmon/spu-insns.h APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ RR 263 arch/powerpc/xmon/spu-insns.h APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ RR 264 arch/powerpc/xmon/spu-insns.h APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ RR 265 arch/powerpc/xmon/spu-insns.h APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ RR 266 arch/powerpc/xmon/spu-insns.h APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ RR 267 arch/powerpc/xmon/spu-insns.h APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ RR 268 arch/powerpc/xmon/spu-insns.h APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ RR 269 arch/powerpc/xmon/spu-insns.h APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ RR 270 arch/powerpc/xmon/spu-insns.h APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ RR 271 arch/powerpc/xmon/spu-insns.h APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ RR 272 arch/powerpc/xmon/spu-insns.h APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ RR 273 arch/powerpc/xmon/spu-insns.h APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ RR 274 arch/powerpc/xmon/spu-insns.h APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ RR 275 arch/powerpc/xmon/spu-insns.h APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ RR 276 arch/powerpc/xmon/spu-insns.h APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ RR 277 arch/powerpc/xmon/spu-insns.h APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ RR 278 arch/powerpc/xmon/spu-insns.h APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */ RR 279 arch/powerpc/xmon/spu-insns.h APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */ RR 280 arch/powerpc/xmon/spu-insns.h APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */ RR 281 arch/powerpc/xmon/spu-insns.h APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */ RR 282 arch/powerpc/xmon/spu-insns.h APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */ RR 283 arch/powerpc/xmon/spu-insns.h APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */ RR 284 arch/powerpc/xmon/spu-insns.h APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */ RR 285 arch/powerpc/xmon/spu-insns.h APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */ RR 286 arch/powerpc/xmon/spu-insns.h APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */ RR 287 arch/powerpc/xmon/spu-insns.h APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */ RR 288 arch/powerpc/xmon/spu-insns.h APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */ RR 289 arch/powerpc/xmon/spu-insns.h APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */ RR 290 arch/powerpc/xmon/spu-insns.h APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */ RR 291 arch/powerpc/xmon/spu-insns.h APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */ RR 292 arch/powerpc/xmon/spu-insns.h APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */ RR 293 arch/powerpc/xmon/spu-insns.h APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */ RR 294 arch/powerpc/xmon/spu-insns.h APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */ RR 295 arch/powerpc/xmon/spu-insns.h APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */ RR 296 arch/powerpc/xmon/spu-insns.h APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */ RR 297 arch/powerpc/xmon/spu-insns.h APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */ RR 298 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */ RR 299 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */ RR 300 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */ RR 301 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */ RR 302 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ RR 303 arch/powerpc/xmon/spu-insns.h APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ RR 304 arch/powerpc/xmon/spu-insns.h APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ RR 305 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ RR 306 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ RR 307 arch/powerpc/xmon/spu-insns.h APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ RR 308 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ RR 309 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ RR 310 arch/powerpc/xmon/spu-insns.h APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ RR 311 arch/powerpc/xmon/spu-insns.h APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ RR 312 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */ RR 313 arch/powerpc/xmon/spu-insns.h APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */ RR 314 arch/powerpc/xmon/spu-insns.h APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */ RR 315 arch/powerpc/xmon/spu-insns.h APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */ RR 316 arch/powerpc/xmon/spu-insns.h APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */ RR 317 arch/powerpc/xmon/spu-insns.h APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */ RR 342 arch/powerpc/xmon/spu-insns.h APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ RR 343 arch/powerpc/xmon/spu-insns.h APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ RR 344 arch/powerpc/xmon/spu-insns.h APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ RR 345 arch/powerpc/xmon/spu-insns.h APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ RR 346 arch/powerpc/xmon/spu-insns.h APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ RR 347 arch/powerpc/xmon/spu-insns.h APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ RR 359 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ RR 360 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ RR 361 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ RR 362 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ RR 363 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ RR 364 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ RR 365 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ RR 366 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ RR 367 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ RR 368 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ RR 369 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ RR 370 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ RR 371 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 372 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 373 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ RR 374 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ RR 375 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 376 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 377 arch/powerpc/xmon/spu-insns.h APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ RR 382 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ RR 383 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 384 arch/powerpc/xmon/spu-insns.h APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ RR 385 arch/powerpc/xmon/spu-insns.h APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 386 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ RR 387 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ RR 388 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 389 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ RR 390 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ RR 391 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ RR 392 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 393 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ RR 232 block/blk-mq-debugfs.c BLK_TAG_ALLOC_NAME(RR), RR 377 drivers/block/paride/bpck.c f = RR(0); RR 257 drivers/block/paride/epat.c cc = RR(0xd); RR 298 drivers/block/paride/epat.c ver = RR(0xb); RR 248 drivers/block/paride/epia.c if (RR(2) != (k^0xaa)) e[j]++; RR 1141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t RR:1; RR 1231 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c cea_channels.channels.RR = speaker_flags.RL_RR; RR 1103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t RR:1; RR 1193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c cea_channels.channels.RR = speaker_flags.RL_RR; RR 549 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG); RR 550 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, LINE_NUMBER); RR 553 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, GLOBAL_ALPHA); RR 555 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG2); RR 557 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG3); RR 560 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DEFAULT_COLOR(i)); RR 561 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TRANS_COLOR(i)); RR 562 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, SIZE_MGR(i)); RR 565 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TIMING_H(i)); RR 566 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TIMING_V(i)); RR 567 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, POL_FREQ(i)); RR 568 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DIVISORo(i)); RR 570 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE1(i)); RR 571 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE2(i)); RR 572 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE3(i)); RR 575 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_R(i)); RR 576 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_G(i)); RR 577 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_B(i)); RR 582 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA0(i)); RR 583 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA1(i)); RR 584 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_POSITION(i)); RR 585 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_SIZE(i)); RR 586 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ATTRIBUTES(i)); RR 587 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIFO_THRESHOLD(i)); RR 588 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ROW_INC(i)); RR 589 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PIXEL_INC(i)); RR 591 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PRELOAD(i)); RR 593 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_WINDOW_SKIP(i)); RR 594 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_TABLE_BA(i)); RR 597 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR(i)); RR 598 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PICTURE_SIZE(i)); RR 599 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU0(i)); RR 600 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU1(i)); RR 603 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_H(i, j)); RR 606 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_HV(i, j)); RR 609 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_CONV_COEF(i, j)); RR 613 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_V(i, j)); RR 617 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA0_UV(i)); RR 618 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA1_UV(i)); RR 619 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR2(i)); RR 620 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU2_0(i)); RR 621 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU2_1(i)); RR 624 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_H2(i, j)); RR 627 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_HV2(i, j)); RR 630 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_V2(i, j)); RR 633 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ATTRIBUTES2(i)); RR 637 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DIVISOR); RR 640 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL); RR 642 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL2); RR 644 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL3); RR 652 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, IRQENABLE); RR 133 drivers/gpu/drm/omapdrm/dss/dss.c RR(dss, CONTROL); RR 136 drivers/gpu/drm/omapdrm/dss/dss.c RR(dss, SDI_CONTROL); RR 137 drivers/gpu/drm/omapdrm/dss/dss.c RR(dss, PLL_CONTROL); RR 457 drivers/isdn/mISDN/layer2.c return data[0] == RR; RR 1128 drivers/isdn/mISDN/layer2.c enquiry_cr(l2, RR, RSP, 1); RR 1138 drivers/isdn/mISDN/layer2.c enquiry_cr(l2, RR, CMD, 1); RR 1187 drivers/isdn/mISDN/layer2.c int PollFlag, rsp, typ = RR; RR 1226 drivers/isdn/mISDN/layer2.c } else if ((nr == l2->vs) && (typ == RR)) { RR 1233 drivers/isdn/mISDN/layer2.c if (typ != RR) RR 1237 drivers/isdn/mISDN/layer2.c if (skb_queue_len(&l2->i_queue) && (typ == RR)) RR 1340 drivers/isdn/mISDN/layer2.c enquiry_cr(l2, RR, RSP, 0); RR 1734 drivers/isdn/mISDN/layer2.c enquiry_cr(l2, RR, RSP, 0); RR 480 drivers/tty/n_gsm.c case RR: RR 405 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONFIG); RR 406 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(LINE_NUMBER); RR 409 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(GLOBAL_ALPHA); RR 411 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONFIG2); RR 413 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONFIG3); RR 416 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DEFAULT_COLOR(i)); RR 417 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(TRANS_COLOR(i)); RR 418 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(SIZE_MGR(i)); RR 421 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(TIMING_H(i)); RR 422 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(TIMING_V(i)); RR 423 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(POL_FREQ(i)); RR 424 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DIVISORo(i)); RR 426 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DATA_CYCLE1(i)); RR 427 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DATA_CYCLE2(i)); RR 428 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DATA_CYCLE3(i)); RR 431 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CPR_COEF_R(i)); RR 432 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CPR_COEF_G(i)); RR 433 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CPR_COEF_B(i)); RR 438 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_BA0(i)); RR 439 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_BA1(i)); RR 440 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_POSITION(i)); RR 441 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_SIZE(i)); RR 442 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ATTRIBUTES(i)); RR 443 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIFO_THRESHOLD(i)); RR 444 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ROW_INC(i)); RR 445 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_PIXEL_INC(i)); RR 447 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_PRELOAD(i)); RR 449 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_WINDOW_SKIP(i)); RR 450 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_TABLE_BA(i)); RR 453 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR(i)); RR 454 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_PICTURE_SIZE(i)); RR 455 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ACCU0(i)); RR 456 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ACCU1(i)); RR 459 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_H(i, j)); RR 462 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_HV(i, j)); RR 465 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_CONV_COEF(i, j)); RR 469 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_V(i, j)); RR 473 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_BA0_UV(i)); RR 474 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_BA1_UV(i)); RR 475 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR2(i)); RR 476 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ACCU2_0(i)); RR 477 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ACCU2_1(i)); RR 480 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_H2(i, j)); RR 483 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_HV2(i, j)); RR 486 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_FIR_COEF_V2(i, j)); RR 489 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(OVL_ATTRIBUTES2(i)); RR 493 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(DIVISOR); RR 496 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONTROL); RR 498 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONTROL2); RR 500 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(CONTROL3); RR 508 drivers/video/fbdev/omap2/omapfb/dss/dispc.c RR(IRQENABLE); RR 152 drivers/video/fbdev/omap2/omapfb/dss/dss.c RR(CONTROL); RR 156 drivers/video/fbdev/omap2/omapfb/dss/dss.c RR(SDI_CONTROL); RR 157 drivers/video/fbdev/omap2/omapfb/dss/dss.c RR(PLL_CONTROL); RR 241 fs/isofs/rock.c if ((rr->u.RR.flags[0] & RR_NM) == 0) RR 358 fs/isofs/rock.c if ((rr->u.RR.flags[0] & RR 752 fs/isofs/rock.c if ((rr->u.RR.flags[0] & RR_SL) == 0) RR 104 fs/isofs/rock.h struct RR_RR_s RR; RR 66 sound/hda/hdmi_chmap.c [3] = RL | RR, RR 127 sound/hda/hdmi_chmap.c { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, RR 129 sound/hda/hdmi_chmap.c { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, RR 131 sound/hda/hdmi_chmap.c { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, RR 133 sound/hda/hdmi_chmap.c { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, RR 135 sound/hda/hdmi_chmap.c { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, RR 137 sound/hda/hdmi_chmap.c { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, RR 144 sound/hda/hdmi_chmap.c { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, RR 145 sound/hda/hdmi_chmap.c { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, RR 146 sound/hda/hdmi_chmap.c { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, RR 147 sound/hda/hdmi_chmap.c { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, RR 148 sound/hda/hdmi_chmap.c { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, RR 149 sound/hda/hdmi_chmap.c { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, RR 158 sound/hda/hdmi_chmap.c { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, RR 159 sound/hda/hdmi_chmap.c { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, RR 160 sound/hda/hdmi_chmap.c { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, RR 161 sound/hda/hdmi_chmap.c { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, RR 162 sound/hda/hdmi_chmap.c { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, RR 163 sound/hda/hdmi_chmap.c { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, RR 164 sound/hda/hdmi_chmap.c { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, RR 165 sound/hda/hdmi_chmap.c { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, RR 166 sound/hda/hdmi_chmap.c { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, RR 167 sound/hda/hdmi_chmap.c { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, RR 168 sound/hda/hdmi_chmap.c { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, RR 169 sound/hda/hdmi_chmap.c { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, RR 170 sound/hda/hdmi_chmap.c { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, RR 171 sound/hda/hdmi_chmap.c { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, RR 172 sound/hda/hdmi_chmap.c { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, RR 173 sound/hda/hdmi_chmap.c { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, RR 174 sound/hda/hdmi_chmap.c { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, RR 175 sound/hda/hdmi_chmap.c { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, RR 176 sound/hda/hdmi_chmap.c { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, RR 177 sound/hda/hdmi_chmap.c { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, RR 178 sound/hda/hdmi_chmap.c { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, RR 179 sound/hda/hdmi_chmap.c { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, RR 399 sound/hda/hdmi_chmap.c { SNDRV_CHMAP_RR, RR }, RR 207 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR}, RR 210 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR }, RR 213 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR }, RR 216 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR }, RR 219 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | RC }, RR 222 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, RR 235 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RC | RL | RR }, RR 237 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | RC }, RR 239 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | RC }, RR 241 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR | RLC | RRC }, RR 243 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | RLC | RRC }, RR 245 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | RLC | RRC }, RR 263 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR | FLC | FRC }, RR 265 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | FLC | FRC }, RR 267 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | FLC | FRC }, RR 269 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, RR 315 sound/soc/codecs/hdmi-codec.c [0] = FL | FR, [1] = LFE, [2] = FC, [3] = RL | RR, RR 63 sound/x86/intel_hdmi_audio.c [3] = RL | RR, RR 85 sound/x86/intel_hdmi_audio.c { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, RR 87 sound/x86/intel_hdmi_audio.c { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, RR 89 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, RR 91 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, RR 93 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, RR 95 sound/x86/intel_hdmi_audio.c { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, RR 102 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, RR 103 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, RR 104 sound/x86/intel_hdmi_audio.c { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, RR 105 sound/x86/intel_hdmi_audio.c { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, RR 106 sound/x86/intel_hdmi_audio.c { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, RR 107 sound/x86/intel_hdmi_audio.c { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, RR 116 sound/x86/intel_hdmi_audio.c { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, RR 117 sound/x86/intel_hdmi_audio.c { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, RR 118 sound/x86/intel_hdmi_audio.c { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, RR 119 sound/x86/intel_hdmi_audio.c { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, RR 126 sound/x86/intel_hdmi_audio.c { SNDRV_CHMAP_RR, 0x05, RR },