RLC_LB_CNTL 2432 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); RLC_LB_CNTL 1573 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); RLC_LB_CNTL 1574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); RLC_LB_CNTL 1622 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); RLC_LB_CNTL 1623 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); RLC_LB_CNTL 1632 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); RLC_LB_CNTL 5788 drivers/gpu/drm/radeon/cik.c tmp = RREG32(RLC_LB_CNTL); RLC_LB_CNTL 5793 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTL, tmp); RLC_LB_CNTL 5949 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTL, 0x80000004); RLC_LB_CNTL 5852 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_LB_CNTL); RLC_LB_CNTL 5857 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTL, tmp); RLC_LB_CNTL 5882 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTL, 0);