RLC_AUTO_PG_CTRL 2777 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); RLC_AUTO_PG_CTRL 2779 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); RLC_AUTO_PG_CTRL 4060 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); RLC_AUTO_PG_CTRL 6520 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 6523 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); RLC_AUTO_PG_CTRL 6530 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 6533 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); RLC_AUTO_PG_CTRL 6668 drivers/gpu/drm/radeon/cik.c data = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 6671 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); RLC_AUTO_PG_CTRL 5267 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 5269 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp); RLC_AUTO_PG_CTRL 5271 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 5273 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp); RLC_AUTO_PG_CTRL 5291 drivers/gpu/drm/radeon/si.c tmp = RREG32(RLC_AUTO_PG_CTRL); RLC_AUTO_PG_CTRL 5296 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp);