RISCV_OP_UNSUPP    45 arch/riscv/kernel/perf_event.c 	[PERF_COUNT_HW_CACHE_REFERENCES]	= RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    46 arch/riscv/kernel/perf_event.c 	[PERF_COUNT_HW_CACHE_MISSES]		= RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    47 arch/riscv/kernel/perf_event.c 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    48 arch/riscv/kernel/perf_event.c 	[PERF_COUNT_HW_BRANCH_MISSES]		= RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    49 arch/riscv/kernel/perf_event.c 	[PERF_COUNT_HW_BUS_CYCLES]		= RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    58 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    59 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    62 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    63 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    66 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    67 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    72 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    73 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    76 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    77 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    80 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    81 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    86 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    87 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    90 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    91 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    94 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP    95 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   100 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] =  RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   101 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] =  RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   104 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   105 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   108 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   109 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   114 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   115 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   118 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   119 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   122 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   123 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   128 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   129 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   132 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   133 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   136 arch/riscv/kernel/perf_event.c 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   137 arch/riscv/kernel/perf_event.c 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
RISCV_OP_UNSUPP   172 arch/riscv/kernel/perf_event.c 	if (code == RISCV_OP_UNSUPP)