RING_START 1206 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_READ(engine, RING_START)); RING_START 1534 drivers/gpu/drm/i915/gt/intel_engine_cs.c u32 ring = ENGINE_READ(rq->engine, RING_START); RING_START 135 drivers/gpu/drm/i915/gt/intel_hangcheck.c hc->ring = ENGINE_READ(engine, RING_START); RING_START 849 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); RING_START 3220 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); RING_START 658 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_START)); RING_START 667 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_START)); RING_START 689 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); RING_START 715 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_START), RING_START 1903 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); RING_START 582 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start; RING_START 1175 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_START(base), 0); RING_START 1100 drivers/gpu/drm/i915/i915_gpu_error.c ee->start = ENGINE_READ(engine, RING_START);