RING_REG         1882 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
RING_REG         1886 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
RING_REG         1890 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
RING_REG         1907 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
RING_REG         2745 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_F(RING_REG, 4, F_RO, 0,
RING_REG         2751 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
RING_REG         2755 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
RING_REG         2760 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
RING_REG         2764 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
RING_REG         2768 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
RING_REG         2787 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);