RING_MI_MODE      858 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	const i915_reg_t mode = RING_MI_MODE(base);
RING_MI_MODE      887 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
RING_MI_MODE     1026 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	    !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
RING_MI_MODE     1216 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_MI_MODE),
RING_MI_MODE     1217 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
RING_MI_MODE     2333 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
RING_MI_MODE     2345 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
RING_MI_MODE      580 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
RING_MI_MODE      607 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			     RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
RING_MI_MODE      609 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 					    RING_MI_MODE(engine->mmio_base),
RING_MI_MODE      723 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			     RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
RING_MI_MODE     2158 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
RING_MI_MODE     1911 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
RING_MI_MODE       69 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
RING_MI_MODE      121 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
RING_MI_MODE     1105 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->mode = ENGINE_READ(engine, RING_MI_MODE);
RING_MI_MODE      206 drivers/gpu/drm/i915/i915_pmu.c 			val = ENGINE_READ_FW(engine, RING_MI_MODE);