RING_FORCE_TO_NONPRIV 1246 drivers/gpu/drm/i915/gt/intel_workarounds.c 				   RING_FORCE_TO_NONPRIV(base, i),
RING_FORCE_TO_NONPRIV 1252 drivers/gpu/drm/i915/gt/intel_workarounds.c 				   RING_FORCE_TO_NONPRIV(base, i),
RING_FORCE_TO_NONPRIV  135 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
RING_FORCE_TO_NONPRIV   49 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
RING_FORCE_TO_NONPRIV   50 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
RING_FORCE_TO_NONPRIV   51 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
RING_FORCE_TO_NONPRIV   52 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
RING_FORCE_TO_NONPRIV   53 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
RING_FORCE_TO_NONPRIV   54 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
RING_FORCE_TO_NONPRIV   55 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
RING_FORCE_TO_NONPRIV   56 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
RING_FORCE_TO_NONPRIV   57 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
RING_FORCE_TO_NONPRIV   58 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
RING_FORCE_TO_NONPRIV   59 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
RING_FORCE_TO_NONPRIV   60 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
RING_FORCE_TO_NONPRIV   81 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
RING_FORCE_TO_NONPRIV   82 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
RING_FORCE_TO_NONPRIV   83 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
RING_FORCE_TO_NONPRIV   84 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
RING_FORCE_TO_NONPRIV   85 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
RING_FORCE_TO_NONPRIV   86 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
RING_FORCE_TO_NONPRIV   87 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
RING_FORCE_TO_NONPRIV   88 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
RING_FORCE_TO_NONPRIV   89 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
RING_FORCE_TO_NONPRIV   90 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
RING_FORCE_TO_NONPRIV   91 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
RING_FORCE_TO_NONPRIV   92 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */