RING_CTL 1212 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_READ(engine, RING_CTL), RING_CTL 1213 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); RING_CTL 120 drivers/gpu/drm/i915/gt/intel_hangcheck.c tmp = ENGINE_READ(engine, RING_CTL); RING_CTL 124 drivers/gpu/drm/i915/gt/intel_hangcheck.c ENGINE_WRITE(engine, RING_CTL, tmp); RING_CTL 850 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); RING_CTL 3221 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), RING_CTL 633 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_WRITE(engine, RING_CTL, 0); RING_CTL 655 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_CTL), RING_CTL 664 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_CTL), RING_CTL 701 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); RING_CTL 705 drivers/gpu/drm/i915/gt/intel_ringbuffer.c RING_CTL(engine->mmio_base), RING_CTL 711 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_CTL), RING_CTL 712 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_READ(engine, RING_CTL) & RING_VALID, RING_CTL 773 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_write_fw(uncore, RING_CTL(base), 0); RING_CTL 1901 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); RING_CTL 1172 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_CTL(base), 0); RING_CTL 1103 drivers/gpu/drm/i915/i915_gpu_error.c ee->ctl = ENGINE_READ(engine, RING_CTL); RING_CTL 188 drivers/gpu/drm/i915/i915_pmu.c val = ENGINE_READ_FW(engine, RING_CTL);