RING_BBADDR_UDW   847 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
RING_BBADDR_UDW   852 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
RING_BBADDR_UDW  3223 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
RING_BBADDR_UDW  3136 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
RING_BBADDR_UDW  1087 drivers/gpu/drm/i915/i915_gpu_error.c 			ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;