A_IMR_CPU1_BASE    22 arch/mips/sibyte/sb1250/smp.c 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
A_IMR_CPU1_BASE    27 arch/mips/sibyte/sb1250/smp.c 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
A_IMR_CPU1_BASE    32 arch/mips/sibyte/sb1250/smp.c 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)