A_IMR_CPU0_BASE 703 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) A_IMR_CPU0_BASE 730 arch/mips/include/asm/sibyte/sb1250_regs.h (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) A_IMR_CPU0_BASE 21 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), A_IMR_CPU0_BASE 26 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), A_IMR_CPU0_BASE 31 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),