AZX_REG_ML_LCTL   173 sound/hda/ext/hdac_ext_controller.c 		val = readl(link->ml_addr + AZX_REG_ML_LCTL);
AZX_REG_ML_LCTL   193 sound/hda/ext/hdac_ext_controller.c 	snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL,
AZX_REG_ML_LCTL   206 sound/hda/ext/hdac_ext_controller.c 	snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
AZX_REG_ML_LCTL   222 sound/hda/ext/hdac_ext_controller.c 		snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
AZX_REG_ML_LCTL   243 sound/hda/ext/hdac_ext_controller.c 		snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
AZX_REG_ML_LCTL   528 sound/pci/hda/hda_intel.c 	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
AZX_REG_ML_LCTL   531 sound/pci/hda/hda_intel.c 	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
AZX_REG_ML_LCTL   535 sound/pci/hda/hda_intel.c 		if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
AZX_REG_ML_LCTL   552 sound/pci/hda/hda_intel.c 	val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
AZX_REG_ML_LCTL   574 sound/pci/hda/hda_intel.c 	writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);