RENDER_RING_BASE 76 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 1, .base = RENDER_RING_BASE } RENDER_RING_BASE 65 drivers/gpu/drm/i915/gt/intel_gt.c clear_register(uncore, IPEIR(RENDER_RING_BASE)); RENDER_RING_BASE 213 drivers/gpu/drm/i915/gt/intel_gt.c RING_HEAD(RENDER_RING_BASE)); RENDER_RING_BASE 1836 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ RENDER_RING_BASE 1895 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); RENDER_RING_BASE 49 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ RENDER_RING_BASE 50 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ RENDER_RING_BASE 51 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ RENDER_RING_BASE 52 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ RENDER_RING_BASE 53 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ RENDER_RING_BASE 54 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ RENDER_RING_BASE 55 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ RENDER_RING_BASE 56 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ RENDER_RING_BASE 57 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ RENDER_RING_BASE 58 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ RENDER_RING_BASE 59 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ RENDER_RING_BASE 60 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ RENDER_RING_BASE 81 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ RENDER_RING_BASE 82 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ RENDER_RING_BASE 83 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ RENDER_RING_BASE 84 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ RENDER_RING_BASE 85 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ RENDER_RING_BASE 86 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ RENDER_RING_BASE 87 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ RENDER_RING_BASE 88 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ RENDER_RING_BASE 89 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ RENDER_RING_BASE 90 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ RENDER_RING_BASE 91 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ RENDER_RING_BASE 92 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ RENDER_RING_BASE 603 drivers/gpu/drm/i915/i915_cmd_parser.c REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), RENDER_RING_BASE 661 drivers/gpu/drm/i915/i915_cmd_parser.c REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), RENDER_RING_BASE 668 drivers/gpu/drm/i915/i915_cmd_parser.c REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), RENDER_RING_BASE 1548 drivers/gpu/drm/i915/i915_gpu_error.c error->ccid = intel_uncore_read(uncore, CCID(RENDER_RING_BASE)); RENDER_RING_BASE 2410 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) RENDER_RING_BASE 2411 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) RENDER_RING_BASE 2412 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) RENDER_RING_BASE 915 drivers/gpu/drm/i915/intel_uncore.c RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ RENDER_RING_BASE 925 drivers/gpu/drm/i915/intel_uncore.c RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ RENDER_RING_BASE 1808 drivers/gpu/drm/i915/intel_uncore.c .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), RENDER_RING_BASE 1809 drivers/gpu/drm/i915/intel_uncore.c .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),