REM 70 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ REM 71 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ REM 73 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ REM 75 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ REM 93 arch/x86/events/intel/ds.c pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); REM 94 arch/x86/events/intel/ds.c pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); REM 95 arch/x86/events/intel/ds.c pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); REM 96 arch/x86/events/intel/ds.c pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);