REG_UPDATE_5       54 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE_5(DC_I2C_CONTROL,
REG_UPDATE_5      197 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE_5(DC_I2C_TRANSACTION0,
REG_UPDATE_5      205 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE_5(DC_I2C_TRANSACTION1,
REG_UPDATE_5      213 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE_5(DC_I2C_TRANSACTION2,
REG_UPDATE_5      221 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE_5(DC_I2C_TRANSACTION3,
REG_UPDATE_5      580 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE_5(HDMI_CONTROL,
REG_UPDATE_5     1046 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE_5(HDMI_CONTROL,
REG_UPDATE_5     1522 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE_5(DP_SEC_CNTL,
REG_UPDATE_5       74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
REG_UPDATE_5       98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
REG_UPDATE_5       70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
REG_UPDATE_5      871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
REG_UPDATE_5     1098 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
REG_UPDATE_5     1108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
REG_UPDATE_5     1118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
REG_UPDATE_5     1012 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE_5(HDMI_CONTROL,
REG_UPDATE_5     1461 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE_5(DP_SEC_CNTL,
REG_UPDATE_5       99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE_5(OTG_GSL_CONTROL,