REG_UPDATE_4      221 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	value = REG_UPDATE_4(AUX_SW_DATA,
REG_UPDATE_4      176 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE_4      585 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE_4      154 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE_4(DP_DPHY_CNTL,
REG_UPDATE_4      497 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
REG_UPDATE_4      156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE_4(DCSURF_TILING_CONFIG,
REG_UPDATE_4      408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
REG_UPDATE_4      518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
REG_UPDATE_4      126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE_4(DP_DPHY_CNTL,
REG_UPDATE_4      882 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
REG_UPDATE_4      959 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
REG_UPDATE_4     1059 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
REG_UPDATE_4      315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE_4(DCSURF_TILING_CONFIG,
REG_UPDATE_4      406 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
REG_UPDATE_4      591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE_4(CURSOR_CONTROL,
REG_UPDATE_4      748 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
REG_UPDATE_4      239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_UPDATE_4(DPG_CONTROL,
REG_UPDATE_4       99 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 		REG_UPDATE_4(DCHVM_CLK_CTRL,