REG_UPDATE         69 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c 	REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
REG_UPDATE         78 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c 	REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
REG_UPDATE        127 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
REG_UPDATE        139 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
REG_UPDATE         78 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        188 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
REG_UPDATE        191 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
REG_UPDATE        223 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
REG_UPDATE        231 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
REG_UPDATE        234 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        272 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
REG_UPDATE        275 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
REG_UPDATE        278 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL1_PWM_USER_LEVEL,
REG_UPDATE        329 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        373 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
REG_UPDATE        405 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
REG_UPDATE        408 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
REG_UPDATE        823 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
REG_UPDATE        827 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
REG_UPDATE        845 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
REG_UPDATE        855 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
REG_UPDATE        859 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
REG_UPDATE        862 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
REG_UPDATE        905 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 	REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
REG_UPDATE         67 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
REG_UPDATE        142 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
REG_UPDATE        198 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
REG_UPDATE        255 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
REG_UPDATE        762 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	REG_UPDATE(RESYNC_CNTL,
REG_UPDATE        775 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(RESYNC_CNTL,
REG_UPDATE        779 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(RESYNC_CNTL,
REG_UPDATE        783 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(RESYNC_CNTL,
REG_UPDATE        787 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(RESYNC_CNTL,
REG_UPDATE        836 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(PIXCLK_RESYNC_CNTL,
REG_UPDATE        919 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
REG_UPDATE        103 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
REG_UPDATE        116 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
REG_UPDATE        135 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        138 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        142 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        185 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        189 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        193 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        197 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        261 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG,
REG_UPDATE        265 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        308 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
REG_UPDATE        311 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        360 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        364 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        398 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        402 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        469 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        473 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        492 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
REG_UPDATE        505 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
REG_UPDATE        531 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        534 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
REG_UPDATE        538 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        594 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        598 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        602 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        606 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        623 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
REG_UPDATE        632 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
REG_UPDATE        675 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG,
REG_UPDATE        679 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        708 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
REG_UPDATE        711 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        746 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
REG_UPDATE        749 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE        769 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
REG_UPDATE        772 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
REG_UPDATE         43 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 	REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
REG_UPDATE        117 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 	REG_UPDATE(BLND_CONTROL[blnd_inst],
REG_UPDATE        132 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
REG_UPDATE        140 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(DCFEV_CLOCK_CONTROL,
REG_UPDATE        171 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
REG_UPDATE        181 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
REG_UPDATE        192 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
REG_UPDATE         62 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
REG_UPDATE        303 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
REG_UPDATE        306 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
REG_UPDATE        339 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE(DC_I2C_ARBITRATION,
REG_UPDATE        369 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
REG_UPDATE         51 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
REG_UPDATE         55 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
REG_UPDATE         66 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
REG_UPDATE         77 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
REG_UPDATE        136 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
REG_UPDATE        146 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(PRESCALE_GRPH_CONTROL,
REG_UPDATE        162 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_UPDATE(PRESCALE_GRPH_CONTROL,
REG_UPDATE        166 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_UPDATE(INPUT_GAMMA_CONTROL,
REG_UPDATE        186 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
REG_UPDATE        215 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
REG_UPDATE        216 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
REG_UPDATE        143 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
REG_UPDATE        164 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
REG_UPDATE        233 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
REG_UPDATE        407 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
REG_UPDATE        411 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
REG_UPDATE        421 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
REG_UPDATE        442 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
REG_UPDATE        489 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
REG_UPDATE        520 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DP_DPHY_FAST_TRAINING,
REG_UPDATE        523 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DP_DPHY_FAST_TRAINING,
REG_UPDATE        534 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
REG_UPDATE        564 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
REG_UPDATE        576 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
REG_UPDATE        887 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
REG_UPDATE        891 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
REG_UPDATE        896 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
REG_UPDATE        900 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
REG_UPDATE        904 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
REG_UPDATE       1317 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_MSE_SAT_UPDATE,
REG_UPDATE       1365 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
REG_UPDATE        150 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
REG_UPDATE        169 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        183 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        202 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        210 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
REG_UPDATE        215 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        223 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
REG_UPDATE        234 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        252 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
REG_UPDATE        256 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
REG_UPDATE        259 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
REG_UPDATE        514 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
REG_UPDATE        604 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL1,
REG_UPDATE        612 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
REG_UPDATE        642 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
REG_UPDATE        697 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
REG_UPDATE        699 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(
REG_UPDATE        727 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
REG_UPDATE        175 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
REG_UPDATE        208 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_DITHER_RAND_R_SEED,
REG_UPDATE        211 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_DITHER_RAND_G_SEED,
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_DITHER_RAND_B_SEED,
REG_UPDATE        304 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
REG_UPDATE        313 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
REG_UPDATE        443 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_CONTROL,
REG_UPDATE        447 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(CONTROL,
REG_UPDATE        496 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_CONTROL,
REG_UPDATE         78 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
REG_UPDATE         98 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
REG_UPDATE        103 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
REG_UPDATE        144 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        148 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        152 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        156 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        160 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        164 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        168 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        172 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        307 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
REG_UPDATE        311 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
REG_UPDATE        319 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 				REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
REG_UPDATE        327 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
REG_UPDATE        330 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
REG_UPDATE        334 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
REG_UPDATE        338 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
REG_UPDATE        352 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
REG_UPDATE        356 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
REG_UPDATE        360 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
REG_UPDATE        365 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
REG_UPDATE        369 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
REG_UPDATE        529 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
REG_UPDATE        532 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
REG_UPDATE        535 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
REG_UPDATE        539 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
REG_UPDATE        542 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
REG_UPDATE        545 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
REG_UPDATE        590 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
REG_UPDATE        653 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
REG_UPDATE        655 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_UPDATE        657 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
REG_UPDATE        660 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
REG_UPDATE        754 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 				REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
REG_UPDATE        764 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
REG_UPDATE        771 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
REG_UPDATE        793 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
REG_UPDATE        877 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
REG_UPDATE        878 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
REG_UPDATE        879 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
REG_UPDATE        890 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        916 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        939 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
REG_UPDATE        947 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
REG_UPDATE        964 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
REG_UPDATE        993 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
REG_UPDATE        999 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
REG_UPDATE       1001 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
REG_UPDATE       1003 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
REG_UPDATE       1008 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
REG_UPDATE       1012 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
REG_UPDATE       1027 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
REG_UPDATE       1037 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
REG_UPDATE       1353 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
REG_UPDATE       1375 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_UPDATE       1400 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
REG_UPDATE       1403 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
REG_UPDATE       1406 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
REG_UPDATE       1409 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
REG_UPDATE       1412 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
REG_UPDATE       1415 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
REG_UPDATE       1429 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
REG_UPDATE       1461 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_UPDATE       1470 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_UPDATE       1473 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
REG_UPDATE       1485 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
REG_UPDATE       1504 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
REG_UPDATE       1512 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE       1533 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE       1543 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
REG_UPDATE       1592 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
REG_UPDATE       1593 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
REG_UPDATE       1602 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
REG_UPDATE        127 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_UPDATE(SCL_MODE, SCL_MODE, 0);
REG_UPDATE        136 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_MODE, 1);
REG_UPDATE        138 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_MODE, 2);
REG_UPDATE        141 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
REG_UPDATE        397 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);
REG_UPDATE        399 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
REG_UPDATE       1148 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_PWR_CTRL,
REG_UPDATE       1151 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
REG_UPDATE       1181 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
REG_UPDATE       1202 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_PWR_CTRL,
REG_UPDATE       1205 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
REG_UPDATE        208 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BASE,
REG_UPDATE        211 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BOT,
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_TOP,
REG_UPDATE        219 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BASE,
REG_UPDATE        222 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BOT,
REG_UPDATE        225 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_TOP,
REG_UPDATE        230 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BASE,
REG_UPDATE        233 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_BOT,
REG_UPDATE        236 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		REG_UPDATE(DCHUB_AGP_TOP,
REG_UPDATE        280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
REG_UPDATE        281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
REG_UPDATE        283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
REG_UPDATE        284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
REG_UPDATE        399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
REG_UPDATE        420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE        422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR0_CONTROL,
REG_UPDATE        440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR0_COLOR0,
REG_UPDATE        442 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR0_COLOR1,
REG_UPDATE        485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_UPDATE(CURSOR0_CONTROL,
REG_UPDATE        497 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
REG_UPDATE        498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
REG_UPDATE        515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 			REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
REG_UPDATE        517 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
REG_UPDATE        374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
REG_UPDATE        376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
REG_UPDATE        607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);
REG_UPDATE        608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
REG_UPDATE        621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
REG_UPDATE        624 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
REG_UPDATE        627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
REG_UPDATE        642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
REG_UPDATE        644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
REG_UPDATE        678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
REG_UPDATE        679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
REG_UPDATE        681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
REG_UPDATE        788 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
REG_UPDATE        790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
REG_UPDATE        792 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
REG_UPDATE        794 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
REG_UPDATE        796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
REG_UPDATE        804 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
REG_UPDATE        819 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
REG_UPDATE        829 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);
REG_UPDATE        541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
REG_UPDATE        700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
REG_UPDATE         78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
REG_UPDATE         88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
REG_UPDATE         91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
REG_UPDATE         94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
REG_UPDATE         95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
REG_UPDATE        618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
REG_UPDATE        620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
REG_UPDATE        647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
REG_UPDATE        650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
REG_UPDATE        653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
REG_UPDATE        656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
REG_UPDATE        659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
REG_UPDATE        666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
REG_UPDATE        669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
REG_UPDATE        672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
REG_UPDATE        678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
REG_UPDATE        681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
REG_UPDATE        684 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
REG_UPDATE        709 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
REG_UPDATE        719 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	REG_UPDATE(DCHUBBUB_SOFT_RESET,
REG_UPDATE         74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL,
REG_UPDATE         77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE         86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL,
REG_UPDATE        107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
REG_UPDATE        115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
REG_UPDATE        261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCSURF_FLIP_CONTROL,
REG_UPDATE        353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
REG_UPDATE        354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
REG_UPDATE        358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
REG_UPDATE        359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
REG_UPDATE        548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(HUBPRET_CONTROL,
REG_UPDATE       1102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
REG_UPDATE       1104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(CURSOR_SURFACE_ADDRESS,
REG_UPDATE       1183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE       1204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
REG_UPDATE       1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
REG_UPDATE        451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
REG_UPDATE        452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
REG_UPDATE        453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
REG_UPDATE        454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
REG_UPDATE        457 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
REG_UPDATE        458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
REG_UPDATE        459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
REG_UPDATE        460 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
REG_UPDATE        492 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
REG_UPDATE        493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
REG_UPDATE        511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN1_PG_CONFIG,
REG_UPDATE        519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN3_PG_CONFIG,
REG_UPDATE        527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN5_PG_CONFIG,
REG_UPDATE        535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN7_PG_CONFIG,
REG_UPDATE        563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN0_PG_CONFIG,
REG_UPDATE        571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN2_PG_CONFIG,
REG_UPDATE        579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN4_PG_CONFIG,
REG_UPDATE        587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DOMAIN6_PG_CONFIG,
REG_UPDATE       1194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_UPDATE       1203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
REG_UPDATE       1299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
REG_UPDATE        115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
REG_UPDATE        136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
REG_UPDATE        205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
REG_UPDATE        378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
REG_UPDATE        382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
REG_UPDATE        392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
REG_UPDATE        413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
REG_UPDATE        499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
REG_UPDATE        508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DP_DPHY_FAST_TRAINING,
REG_UPDATE        511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DP_DPHY_FAST_TRAINING,
REG_UPDATE        522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
REG_UPDATE        552 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
REG_UPDATE        564 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
REG_UPDATE        881 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
REG_UPDATE        885 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
REG_UPDATE        890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
REG_UPDATE        894 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
REG_UPDATE        898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
REG_UPDATE       1284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_MSE_SAT_UPDATE,
REG_UPDATE       1332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
REG_UPDATE        210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
REG_UPDATE        223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
REG_UPDATE        234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
REG_UPDATE        279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
REG_UPDATE        283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
REG_UPDATE        303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
REG_UPDATE        363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
REG_UPDATE        381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
REG_UPDATE        168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
REG_UPDATE        171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
REG_UPDATE        174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
REG_UPDATE        286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
REG_UPDATE        320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
REG_UPDATE        322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);
REG_UPDATE        330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);
REG_UPDATE        332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
REG_UPDATE        352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width);
REG_UPDATE        360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation);
REG_UPDATE        363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num);
REG_UPDATE        368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
REG_UPDATE        373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
REG_UPDATE        382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
REG_UPDATE        198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OTG_H_SYNC_A_CNTL,
REG_UPDATE        239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OTG_V_SYNC_A_CNTL,
REG_UPDATE        253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE(OTG_INTERLACE_CONTROL,
REG_UPDATE        256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE(OTG_INTERLACE_CONTROL,
REG_UPDATE        261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(CONTROL,
REG_UPDATE        291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OTG_H_TIMING_CNTL,
REG_UPDATE        343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
REG_UPDATE        453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
REG_UPDATE        457 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(CONTROL,
REG_UPDATE        480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(CONTROL,
REG_UPDATE       1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE(OTG_STEREO_CONTROL,
REG_UPDATE       1196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE(OTG_STEREO_CONTROL,
REG_UPDATE       1376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
REG_UPDATE         68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
REG_UPDATE         87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
REG_UPDATE         91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
REG_UPDATE        123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
REG_UPDATE        485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
REG_UPDATE        488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
REG_UPDATE        526 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
REG_UPDATE        588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
REG_UPDATE        590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_UPDATE        592 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
REG_UPDATE        595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
REG_UPDATE        657 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
REG_UPDATE        739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
REG_UPDATE        740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
REG_UPDATE        741 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
REG_UPDATE        753 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        774 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
REG_UPDATE        777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
REG_UPDATE        780 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
REG_UPDATE        790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
REG_UPDATE        793 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
REG_UPDATE        832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
REG_UPDATE        836 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
REG_UPDATE        847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        874 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
REG_UPDATE        907 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
REG_UPDATE        924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
REG_UPDATE        958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
REG_UPDATE        964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
REG_UPDATE        966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
REG_UPDATE        975 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
REG_UPDATE        979 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
REG_UPDATE        994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
REG_UPDATE       1004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
REG_UPDATE       1294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
REG_UPDATE       1306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
REG_UPDATE       1310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_UPDATE       1335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
REG_UPDATE       1338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
REG_UPDATE       1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
REG_UPDATE       1344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
REG_UPDATE       1347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
REG_UPDATE       1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
REG_UPDATE       1366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
REG_UPDATE       1400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_UPDATE       1409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_UPDATE       1412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
REG_UPDATE       1424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
REG_UPDATE       1443 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
REG_UPDATE       1451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE       1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE       1483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
REG_UPDATE       1532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
REG_UPDATE       1533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
REG_UPDATE       1542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
REG_UPDATE         90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL,
REG_UPDATE         93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL,
REG_UPDATE        127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1);
REG_UPDATE        130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1);
REG_UPDATE        133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1);
REG_UPDATE        136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1);
REG_UPDATE        139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1);
REG_UPDATE        142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1);
REG_UPDATE         81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
REG_UPDATE         83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(OBUF_MEM_PWR_CTRL,
REG_UPDATE         86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(DSCL_MEM_PWR_CTRL,
REG_UPDATE        122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
REG_UPDATE        123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
REG_UPDATE        124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
REG_UPDATE        125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
REG_UPDATE        211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
REG_UPDATE        212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
REG_UPDATE        213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
REG_UPDATE        219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
REG_UPDATE        239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE        241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(CURSOR0_CONTROL,
REG_UPDATE        255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
REG_UPDATE        256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
REG_UPDATE        257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
REG_UPDATE        258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
REG_UPDATE        259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
REG_UPDATE        260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
REG_UPDATE        326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
REG_UPDATE        328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
REG_UPDATE        330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
REG_UPDATE        331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
REG_UPDATE        333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
REG_UPDATE        334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
REG_UPDATE        336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
REG_UPDATE        337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
REG_UPDATE        339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
REG_UPDATE        340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
REG_UPDATE        365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(CURSOR0_COLOR0,
REG_UPDATE        367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(CURSOR0_COLOR1,
REG_UPDATE         60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
REG_UPDATE         94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
REG_UPDATE         96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
REG_UPDATE        144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
REG_UPDATE        147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
REG_UPDATE        150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
REG_UPDATE        175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,
REG_UPDATE        177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,
REG_UPDATE        414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
REG_UPDATE        416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
REG_UPDATE        903 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
REG_UPDATE        994 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);
REG_UPDATE        229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_UPDATE(DSC_TOP_CONTROL,
REG_UPDATE        244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
REG_UPDATE        247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_UPDATE(DSC_TOP_CONTROL,
REG_UPDATE         83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1);
REG_UPDATE         84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x);
REG_UPDATE         85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y);
REG_UPDATE         86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_WINDOW_SIZE,  CNV_WINDOW_WIDTH,   params->cnv_params.crop_width);
REG_UPDATE         87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_WINDOW_SIZE,  CNV_WINDOW_HEIGHT,  params->cnv_params.crop_height);
REG_UPDATE         89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0);
REG_UPDATE         93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate);
REG_UPDATE         96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc);
REG_UPDATE        118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
REG_UPDATE        127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);
REG_UPDATE        130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, 0);
REG_UPDATE        141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);
REG_UPDATE        144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
REG_UPDATE        147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
REG_UPDATE        148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
REG_UPDATE        181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 1);
REG_UPDATE        192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 0);
REG_UPDATE        218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_STEREO_TYPE,     stereo_params->stereo_type);
REG_UPDATE        219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION,   stereo_params->stereo_eye_select);
REG_UPDATE        220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_STEREO_POLARITY, stereo_params->stereo_polarity);
REG_UPDATE        222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, 0);
REG_UPDATE        232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(CNV_MODE, CNV_NEW_CONTENT, is_new_content);
REG_UPDATE        241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, warmup_params->warmup_en);
REG_UPDATE        242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, warmup_params->warmup_width);
REG_UPDATE        243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, warmup_params->warmup_height);
REG_UPDATE        245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, warmup_params->warmup_data);
REG_UPDATE        246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, warmup_params->warmup_mode);
REG_UPDATE        247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, warmup_params->warmup_depth);
REG_UPDATE        261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH,	params->dest_width);
REG_UPDATE        262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT,	params->dest_height);
REG_UPDATE        265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, 0x40);
REG_UPDATE        266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR,  0x200);
REG_UPDATE        269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_CLAMP_Y_RGB,	WBSCL_CLAMP_UPPER_Y_RGB,	0x3fe);
REG_UPDATE        270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_CLAMP_Y_RGB,	WBSCL_CLAMP_LOWER_Y_RGB,	0x1);
REG_UPDATE        271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_CLAMP_CBCR,	WBSCL_CLAMP_UPPER_CBCR,		0x3fe);
REG_UPDATE        272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_CLAMP_CBCR,	WBSCL_CLAMP_LOWER_CBCR,		0x1);
REG_UPDATE        275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		REG_UPDATE(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, DWB_OUTSIDE_PIX_STRATEGY_EDGE);
REG_UPDATE        753 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma);
REG_UPDATE        756 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1);
REG_UPDATE        757 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1);
REG_UPDATE        779 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int);
REG_UPDATE        780 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac);
REG_UPDATE        781 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int);
REG_UPDATE        782 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac);
REG_UPDATE        833 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma);
REG_UPDATE        836 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1);
REG_UPDATE        837 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1);
REG_UPDATE        860 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, v_init_phase_luma_int);
REG_UPDATE        861 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, v_init_phase_luma_frac);
REG_UPDATE        862 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, v_init_phase_chroma_int);
REG_UPDATE        863 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, v_init_phase_chroma_frac);
REG_UPDATE        412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
REG_UPDATE        415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
REG_UPDATE        419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BASE,
REG_UPDATE        424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BOT,
REG_UPDATE        429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_TOP,
REG_UPDATE        437 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BASE,
REG_UPDATE        442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BOT,
REG_UPDATE        447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_TOP,
REG_UPDATE        455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BASE,
REG_UPDATE        460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_BOT,
REG_UPDATE        465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		REG_UPDATE(DCN_VM_AGP_TOP,
REG_UPDATE        589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
REG_UPDATE        187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
REG_UPDATE        196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(HUBPRET_CONTROL,
REG_UPDATE        438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
REG_UPDATE        582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
REG_UPDATE        584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(CURSOR_SURFACE_ADDRESS,
REG_UPDATE        612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DMDATA_CNTL,
REG_UPDATE        616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
REG_UPDATE        619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DMDATA_CNTL,
REG_UPDATE        628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DMDATA_ADDRESS_HIGH,
REG_UPDATE        631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
REG_UPDATE        638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DMDATA_SW_CNTL,
REG_UPDATE        685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCSURF_FLIP_CONTROL,
REG_UPDATE        689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(VMID_SETTINGS_0,
REG_UPDATE        693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
REG_UPDATE        694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
REG_UPDATE        698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
REG_UPDATE        699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
REG_UPDATE        862 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REG_UPDATE(DCSURF_FLIP_CONTROL2,
REG_UPDATE        882 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
REG_UPDATE       1006 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE       1027 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
REG_UPDATE       1034 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
REG_UPDATE       1041 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
REG_UPDATE         77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
REG_UPDATE         78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
REG_UPDATE         79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
REG_UPDATE         80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
REG_UPDATE         82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
REG_UPDATE         84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
REG_UPDATE         87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
REG_UPDATE         88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
REG_UPDATE         89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
REG_UPDATE         90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
REG_UPDATE         92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
REG_UPDATE         94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
REG_UPDATE         97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
REG_UPDATE         98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
REG_UPDATE         99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
REG_UPDATE        101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
REG_UPDATE        103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
REG_UPDATE        105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
REG_UPDATE        145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
REG_UPDATE        153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
REG_UPDATE        154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_UPDATE        165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
REG_UPDATE        268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN16_PG_CONFIG,
REG_UPDATE        276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN17_PG_CONFIG,
REG_UPDATE        284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN18_PG_CONFIG,
REG_UPDATE        292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN19_PG_CONFIG,
REG_UPDATE        300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN20_PG_CONFIG,
REG_UPDATE        308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN21_PG_CONFIG,
REG_UPDATE        340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN1_PG_CONFIG,
REG_UPDATE        348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN3_PG_CONFIG,
REG_UPDATE        356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN5_PG_CONFIG,
REG_UPDATE        364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN7_PG_CONFIG,
REG_UPDATE        372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN9_PG_CONFIG,
REG_UPDATE        414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN0_PG_CONFIG,
REG_UPDATE        422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN2_PG_CONFIG,
REG_UPDATE        430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN4_PG_CONFIG,
REG_UPDATE        438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN6_PG_CONFIG,
REG_UPDATE        446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_UPDATE(DOMAIN8_PG_CONFIG,
REG_UPDATE       2016 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
REG_UPDATE       2017 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_UPDATE        175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
REG_UPDATE        182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
REG_UPDATE        312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
REG_UPDATE         83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
REG_UPDATE         86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
REG_UPDATE         87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
REG_UPDATE         89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);
REG_UPDATE         92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
REG_UPDATE         93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
REG_UPDATE         95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);
REG_UPDATE         98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
REG_UPDATE         99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
REG_UPDATE        101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0);
REG_UPDATE        104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
REG_UPDATE        105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
REG_UPDATE        107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0);
REG_UPDATE        110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
REG_UPDATE        111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
REG_UPDATE        113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);
REG_UPDATE        116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
REG_UPDATE        117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
REG_UPDATE        119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);
REG_UPDATE        122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
REG_UPDATE        123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
REG_UPDATE        125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);
REG_UPDATE        128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
REG_UPDATE        129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
REG_UPDATE        131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0);
REG_UPDATE        137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
REG_UPDATE        138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
REG_UPDATE        141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
REG_UPDATE        150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch);
REG_UPDATE        159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
REG_UPDATE        164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
REG_UPDATE        166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[0]);
REG_UPDATE        167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
REG_UPDATE        169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[1]);
REG_UPDATE        170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
REG_UPDATE        172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[2]);
REG_UPDATE        173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
REG_UPDATE        175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[3]);
REG_UPDATE        179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
REG_UPDATE        180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
REG_UPDATE        183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
REG_UPDATE        184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
REG_UPDATE        187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
REG_UPDATE        188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
REG_UPDATE        191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
REG_UPDATE        192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
REG_UPDATE        196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
REG_UPDATE        199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
REG_UPDATE        204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE,  params->arbitration_slice);
REG_UPDATE        213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en);
REG_UPDATE        214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en);
REG_UPDATE        215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN,  params->sw_overrun_int_en);
REG_UPDATE        217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN,  params->vce_int_en);
REG_UPDATE        218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN,  params->vce_slice_int_en);
REG_UPDATE        226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1);
REG_UPDATE        234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0);
REG_UPDATE        284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);
REG_UPDATE        289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);
REG_UPDATE        105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_UPDATE(DENORM_CONTROL[opp_id],
REG_UPDATE        319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count);
REG_UPDATE         55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
REG_UPDATE         59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(CONTROL,
REG_UPDATE         81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
REG_UPDATE        114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_GSL_CONTROL,
REG_UPDATE        157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
REG_UPDATE        160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
REG_UPDATE        163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
REG_UPDATE        195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
REG_UPDATE        201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OPTC_WIDTH_CONTROL,
REG_UPDATE        225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_H_TIMING_CNTL,
REG_UPDATE        267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
REG_UPDATE        274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OPTC_WIDTH_CONTROL,
REG_UPDATE        310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(DWB_SOURCE_SELECT,
REG_UPDATE        313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(DWB_SOURCE_SELECT,
REG_UPDATE        354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
REG_UPDATE        383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
REG_UPDATE         83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
REG_UPDATE         90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
REG_UPDATE         97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
REG_UPDATE        104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
REG_UPDATE        111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
REG_UPDATE        118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
REG_UPDATE        125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
REG_UPDATE        132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
REG_UPDATE        151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
REG_UPDATE        226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1);
REG_UPDATE        229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
REG_UPDATE        241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
REG_UPDATE        244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);
REG_UPDATE        256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);
REG_UPDATE        268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, 1);
REG_UPDATE        319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL6,
REG_UPDATE        337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0);
REG_UPDATE        338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);
REG_UPDATE        400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 				REG_UPDATE(DIG_FE_CNTL,
REG_UPDATE        404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DME_CONTROL,
REG_UPDATE        407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DME_CONTROL,
REG_UPDATE        411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,
REG_UPDATE        414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,
REG_UPDATE        416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL,
REG_UPDATE        436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_UPDATE        480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
REG_UPDATE        486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
REG_UPDATE        488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
REG_UPDATE        496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
REG_UPDATE        500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
REG_UPDATE        505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
REG_UPDATE        510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
REG_UPDATE        513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
REG_UPDATE        528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
REG_UPDATE        537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
REG_UPDATE        550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_SEC_FRAMING4,
REG_UPDATE         79 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
REG_UPDATE         93 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
REG_UPDATE         96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
REG_UPDATE        506 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL,
REG_UPDATE        122 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	REG_UPDATE(HUBPRET_CONTROL,
REG_UPDATE        149 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 			REG_UPDATE(gpio.MASK_reg,
REG_UPDATE        155 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 				REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
REG_UPDATE        159 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 				REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
REG_UPDATE        171 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 			REG_UPDATE(dc_gpio_aux_ctrl_5,
REG_UPDATE         54 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 	REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
REG_UPDATE         55 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 	REG_UPDATE(A_reg, A, gpio->store.a);
REG_UPDATE         56 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 	REG_UPDATE(EN_reg, EN, gpio->store.en);
REG_UPDATE        107 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(A_reg, A, value);
REG_UPDATE        114 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(EN_reg, EN, ~value);
REG_UPDATE        151 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(EN_reg, EN, 0);
REG_UPDATE        152 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE        157 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(A_reg, A, 0);
REG_UPDATE        158 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE        163 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(A_reg, A, 0);
REG_UPDATE        164 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
REG_UPDATE        168 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 0);
REG_UPDATE        172 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 0);
REG_UPDATE        383 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h {	uint32_t val = REG_UPDATE(reg, f1, v1); \
REG_UPDATE        387 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h {	uint32_t val = REG_UPDATE(reg, f1, v1); \