REG_SET_FIELD     160 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
REG_SET_FIELD     167 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
REG_SET_FIELD     196 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
REG_SET_FIELD     382 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
REG_SET_FIELD     397 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
REG_SET_FIELD     443 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	       REG_SET_FIELD(m->cp_hqd_eop_rptr,
REG_SET_FIELD     446 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
REG_SET_FIELD     518 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
REG_SET_FIELD     525 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
REG_SET_FIELD     554 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
REG_SET_FIELD     893 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     895 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     897 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     352 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
REG_SET_FIELD     366 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
REG_SET_FIELD     436 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
REG_SET_FIELD     441 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
REG_SET_FIELD     446 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
REG_SET_FIELD     467 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
REG_SET_FIELD     309 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
REG_SET_FIELD     337 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
REG_SET_FIELD     351 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
REG_SET_FIELD     420 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
REG_SET_FIELD     425 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
REG_SET_FIELD     430 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
REG_SET_FIELD     451 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
REG_SET_FIELD     720 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     722 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     724 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     283 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
REG_SET_FIELD     298 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
REG_SET_FIELD     343 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	       REG_SET_FIELD(m->cp_hqd_eop_rptr,
REG_SET_FIELD     346 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
REG_SET_FIELD     417 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
REG_SET_FIELD     424 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
REG_SET_FIELD     453 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
REG_SET_FIELD     760 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     762 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD     764 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
REG_SET_FIELD    1766 drivers/gpu/drm/amd/amdgpu/cik.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
REG_SET_FIELD    1767 drivers/gpu/drm/amd/amdgpu/cik.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
REG_SET_FIELD     379 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     388 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD      65 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
REG_SET_FIELD      66 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD      84 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD      85 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
REG_SET_FIELD     121 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     123 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     130 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
REG_SET_FIELD     131 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     132 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     149 drivers/gpu/drm/amd/amdgpu/cz_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
REG_SET_FIELD     152 drivers/gpu/drm/amd/amdgpu/cz_ih.c 		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
REG_SET_FIELD     197 drivers/gpu/drm/amd/amdgpu/cz_ih.c 		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
REG_SET_FIELD     206 drivers/gpu/drm/amd/amdgpu/cz_ih.c 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     365 drivers/gpu/drm/amd/amdgpu/cz_ih.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
REG_SET_FIELD     244 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
REG_SET_FIELD     315 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
REG_SET_FIELD     317 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
REG_SET_FIELD     349 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
REG_SET_FIELD     355 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
REG_SET_FIELD     359 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
REG_SET_FIELD     362 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
REG_SET_FIELD     394 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
REG_SET_FIELD     445 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
REG_SET_FIELD     447 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
REG_SET_FIELD     453 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
REG_SET_FIELD     455 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
REG_SET_FIELD     490 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
REG_SET_FIELD     531 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     532 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     533 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     534 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
REG_SET_FIELD     536 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     537 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
REG_SET_FIELD     543 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     544 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     545 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
REG_SET_FIELD     546 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     547 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
REG_SET_FIELD     549 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     550 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
REG_SET_FIELD     556 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     557 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     558 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
REG_SET_FIELD     559 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     560 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
REG_SET_FIELD     562 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     563 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
REG_SET_FIELD     623 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
REG_SET_FIELD     627 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
REG_SET_FIELD    1120 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
REG_SET_FIELD    1123 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
REG_SET_FIELD    1124 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
REG_SET_FIELD    1127 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
REG_SET_FIELD    1130 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
REG_SET_FIELD    1131 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
REG_SET_FIELD    1215 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
REG_SET_FIELD    1248 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1250 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1253 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1255 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1297 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1300 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1303 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1306 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1372 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1374 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1376 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1388 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1475 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
REG_SET_FIELD    1478 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
REG_SET_FIELD    1482 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
REG_SET_FIELD    1485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
REG_SET_FIELD    1489 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
REG_SET_FIELD    1492 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
REG_SET_FIELD    1540 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
REG_SET_FIELD    1584 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
REG_SET_FIELD    1596 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
REG_SET_FIELD    1597 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
REG_SET_FIELD    1602 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
REG_SET_FIELD    1603 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
REG_SET_FIELD    1608 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
REG_SET_FIELD    1609 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
REG_SET_FIELD    1617 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
REG_SET_FIELD    1618 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
REG_SET_FIELD    1619 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
REG_SET_FIELD    1624 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
REG_SET_FIELD    1626 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
REG_SET_FIELD    1631 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_SET_FIELD    1636 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
REG_SET_FIELD    1643 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
REG_SET_FIELD    1645 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
REG_SET_FIELD    1650 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_SET_FIELD    1656 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
REG_SET_FIELD    1659 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
REG_SET_FIELD    1661 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
REG_SET_FIELD    1667 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
REG_SET_FIELD    1671 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
REG_SET_FIELD    1675 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
REG_SET_FIELD    1676 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
REG_SET_FIELD    1677 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
REG_SET_FIELD    1678 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
REG_SET_FIELD    1679 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
REG_SET_FIELD    1680 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
REG_SET_FIELD    1708 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
REG_SET_FIELD    1710 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
REG_SET_FIELD    1714 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
REG_SET_FIELD    1719 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
REG_SET_FIELD    1841 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
REG_SET_FIELD    1884 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
REG_SET_FIELD    1885 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1889 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1890 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
REG_SET_FIELD    1892 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1898 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1899 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1901 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1907 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1908 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
REG_SET_FIELD    1910 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1915 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1916 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
REG_SET_FIELD    1918 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1924 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1925 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1927 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1933 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1934 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
REG_SET_FIELD    1936 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1944 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1945 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
REG_SET_FIELD    1947 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1955 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1956 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1957 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
REG_SET_FIELD    1958 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
REG_SET_FIELD    1960 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1979 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
REG_SET_FIELD    1980 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
REG_SET_FIELD    1982 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
REG_SET_FIELD    1984 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
REG_SET_FIELD    1985 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
REG_SET_FIELD    1986 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
REG_SET_FIELD    1988 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
REG_SET_FIELD    1991 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
REG_SET_FIELD    1995 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
REG_SET_FIELD    2004 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
REG_SET_FIELD    2026 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
REG_SET_FIELD    2028 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
REG_SET_FIELD    2086 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
REG_SET_FIELD    2088 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
REG_SET_FIELD    2104 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
REG_SET_FIELD    2105 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
REG_SET_FIELD    2109 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
REG_SET_FIELD    2113 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
REG_SET_FIELD    2117 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
REG_SET_FIELD    2118 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
REG_SET_FIELD    2146 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
REG_SET_FIELD    2147 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
REG_SET_FIELD    2148 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
REG_SET_FIELD    2152 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
REG_SET_FIELD    2153 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
REG_SET_FIELD    2157 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
REG_SET_FIELD    2158 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
REG_SET_FIELD    2162 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
REG_SET_FIELD    2163 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
REG_SET_FIELD    2172 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
REG_SET_FIELD    2276 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
REG_SET_FIELD    2278 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
REG_SET_FIELD    2289 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
REG_SET_FIELD    2305 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
REG_SET_FIELD    2306 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
REG_SET_FIELD    2966 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    2972 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    2995 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3001 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3025 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
REG_SET_FIELD    3030 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
REG_SET_FIELD    3175 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
REG_SET_FIELD    3190 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
REG_SET_FIELD    3205 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
REG_SET_FIELD     262 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
REG_SET_FIELD     333 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
REG_SET_FIELD     335 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
REG_SET_FIELD     367 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
REG_SET_FIELD     373 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
REG_SET_FIELD     377 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
REG_SET_FIELD     380 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
REG_SET_FIELD     411 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
REG_SET_FIELD     461 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
REG_SET_FIELD     463 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
REG_SET_FIELD     469 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
REG_SET_FIELD     471 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
REG_SET_FIELD     516 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
REG_SET_FIELD     557 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     558 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     559 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     560 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
REG_SET_FIELD     562 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     563 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
REG_SET_FIELD     569 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     570 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     571 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
REG_SET_FIELD     572 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     573 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
REG_SET_FIELD     575 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     576 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
REG_SET_FIELD     582 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
REG_SET_FIELD     583 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
REG_SET_FIELD     584 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
REG_SET_FIELD     585 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
REG_SET_FIELD     586 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
REG_SET_FIELD     588 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
REG_SET_FIELD     589 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
REG_SET_FIELD     649 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
REG_SET_FIELD     653 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
REG_SET_FIELD    1146 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
REG_SET_FIELD    1149 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
REG_SET_FIELD    1150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
REG_SET_FIELD    1153 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
REG_SET_FIELD    1156 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
REG_SET_FIELD    1157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
REG_SET_FIELD    1241 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
REG_SET_FIELD    1274 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1276 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1279 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1281 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1323 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1326 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1329 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1332 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1398 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1400 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1402 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1414 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1517 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
REG_SET_FIELD    1520 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
REG_SET_FIELD    1524 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
REG_SET_FIELD    1527 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
REG_SET_FIELD    1531 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
REG_SET_FIELD    1534 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
REG_SET_FIELD    1582 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
REG_SET_FIELD    1626 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
REG_SET_FIELD    1638 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
REG_SET_FIELD    1639 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
REG_SET_FIELD    1644 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
REG_SET_FIELD    1645 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
REG_SET_FIELD    1650 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
REG_SET_FIELD    1651 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
REG_SET_FIELD    1659 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
REG_SET_FIELD    1660 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
REG_SET_FIELD    1661 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
REG_SET_FIELD    1666 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
REG_SET_FIELD    1668 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
REG_SET_FIELD    1673 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_SET_FIELD    1678 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
REG_SET_FIELD    1685 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
REG_SET_FIELD    1687 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
REG_SET_FIELD    1692 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_SET_FIELD    1698 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
REG_SET_FIELD    1701 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
REG_SET_FIELD    1703 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
REG_SET_FIELD    1709 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
REG_SET_FIELD    1713 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
REG_SET_FIELD    1717 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
REG_SET_FIELD    1718 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
REG_SET_FIELD    1719 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
REG_SET_FIELD    1720 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
REG_SET_FIELD    1721 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
REG_SET_FIELD    1722 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
REG_SET_FIELD    1750 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
REG_SET_FIELD    1752 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
REG_SET_FIELD    1756 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
REG_SET_FIELD    1761 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
REG_SET_FIELD    1883 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
REG_SET_FIELD    1926 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
REG_SET_FIELD    1927 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1931 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1932 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
REG_SET_FIELD    1934 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1940 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1941 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1943 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1949 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1950 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
REG_SET_FIELD    1952 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1957 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
REG_SET_FIELD    1958 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
REG_SET_FIELD    1960 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1966 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1967 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1969 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1975 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1976 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
REG_SET_FIELD    1978 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1986 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1987 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
REG_SET_FIELD    1989 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    1997 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
REG_SET_FIELD    1998 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
REG_SET_FIELD    1999 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
REG_SET_FIELD    2000 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
REG_SET_FIELD    2002 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
REG_SET_FIELD    2021 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
REG_SET_FIELD    2022 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
REG_SET_FIELD    2024 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
REG_SET_FIELD    2026 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
REG_SET_FIELD    2027 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
REG_SET_FIELD    2028 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
REG_SET_FIELD    2030 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
REG_SET_FIELD    2033 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
REG_SET_FIELD    2037 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
REG_SET_FIELD    2046 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
REG_SET_FIELD    2068 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
REG_SET_FIELD    2070 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
REG_SET_FIELD    2128 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
REG_SET_FIELD    2130 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
REG_SET_FIELD    2146 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
REG_SET_FIELD    2150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
REG_SET_FIELD    2154 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
REG_SET_FIELD    2182 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
REG_SET_FIELD    2183 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
REG_SET_FIELD    2184 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
REG_SET_FIELD    2188 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
REG_SET_FIELD    2192 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
REG_SET_FIELD    2196 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
REG_SET_FIELD    2205 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
REG_SET_FIELD    2355 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
REG_SET_FIELD    2357 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
REG_SET_FIELD    2368 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
REG_SET_FIELD    2384 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
REG_SET_FIELD    2385 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
REG_SET_FIELD    3092 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3098 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3121 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3127 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
REG_SET_FIELD    3151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
REG_SET_FIELD    3156 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
REG_SET_FIELD    3301 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
REG_SET_FIELD    3316 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
REG_SET_FIELD    3331 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
REG_SET_FIELD    1120 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	       REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
REG_SET_FIELD    1151 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1153 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1156 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1158 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
REG_SET_FIELD    1197 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1199 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1203 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1206 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1210 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1213 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
REG_SET_FIELD    1276 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1278 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1280 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1292 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
REG_SET_FIELD    1384 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
REG_SET_FIELD    1385 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
REG_SET_FIELD    1386 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
REG_SET_FIELD    1401 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
REG_SET_FIELD    1402 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
REG_SET_FIELD    1407 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
REG_SET_FIELD    1410 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
REG_SET_FIELD    1414 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
REG_SET_FIELD    1417 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
REG_SET_FIELD    1421 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
REG_SET_FIELD    1424 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
REG_SET_FIELD    1466 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
REG_SET_FIELD    1486 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
REG_SET_FIELD    1489 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
REG_SET_FIELD    1492 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
REG_SET_FIELD    1514 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
REG_SET_FIELD    1518 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
REG_SET_FIELD    1522 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
REG_SET_FIELD    1526 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
REG_SET_FIELD    1527 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
REG_SET_FIELD    1528 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
REG_SET_FIELD    1529 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
REG_SET_FIELD    1530 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
REG_SET_FIELD    1531 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
REG_SET_FIELD    1535 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
REG_SET_FIELD    1539 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
REG_SET_FIELD    1540 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
REG_SET_FIELD    1544 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
REG_SET_FIELD    1545 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
REG_SET_FIELD    1558 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
REG_SET_FIELD    1572 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
REG_SET_FIELD    1573 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
REG_SET_FIELD    1574 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
REG_SET_FIELD    1575 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
REG_SET_FIELD    1579 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
REG_SET_FIELD    1583 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
REG_SET_FIELD    1587 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
REG_SET_FIELD    1588 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
REG_SET_FIELD    1589 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
REG_SET_FIELD    1590 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
REG_SET_FIELD    1594 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
REG_SET_FIELD    1609 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
REG_SET_FIELD    1613 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
REG_SET_FIELD    1617 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
REG_SET_FIELD    1618 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
REG_SET_FIELD    1619 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
REG_SET_FIELD    1620 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
REG_SET_FIELD     378 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
REG_SET_FIELD     380 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
REG_SET_FIELD     386 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
REG_SET_FIELD     388 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
REG_SET_FIELD     430 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
REG_SET_FIELD    1501 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
REG_SET_FIELD    1504 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
REG_SET_FIELD    1508 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
REG_SET_FIELD    1511 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
REG_SET_FIELD    1514 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
REG_SET_FIELD    1517 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
REG_SET_FIELD    1755 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
REG_SET_FIELD    1757 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
REG_SET_FIELD    1776 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
REG_SET_FIELD    1778 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
REG_SET_FIELD    1780 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
REG_SET_FIELD    1782 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
REG_SET_FIELD    1840 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
REG_SET_FIELD    2252 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2289 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2326 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2363 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2439 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
REG_SET_FIELD    2440 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
REG_SET_FIELD    2441 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
REG_SET_FIELD    2496 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2517 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
REG_SET_FIELD    2518 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
REG_SET_FIELD    2519 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
REG_SET_FIELD    2520 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
REG_SET_FIELD    2566 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2587 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
REG_SET_FIELD    2588 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
REG_SET_FIELD    2589 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
REG_SET_FIELD    2590 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
REG_SET_FIELD    2635 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2656 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
REG_SET_FIELD    2657 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
REG_SET_FIELD    2658 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
REG_SET_FIELD    2659 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
REG_SET_FIELD    2782 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
REG_SET_FIELD    2794 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    2796 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    2799 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    2803 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
REG_SET_FIELD    2832 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    2833 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
REG_SET_FIELD    2835 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
REG_SET_FIELD    2873 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    2874 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
REG_SET_FIELD    2956 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD    2977 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
REG_SET_FIELD    2978 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
REG_SET_FIELD    2979 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
REG_SET_FIELD    3036 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
REG_SET_FIELD    3037 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
REG_SET_FIELD    3038 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
REG_SET_FIELD    3043 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
REG_SET_FIELD    3049 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
REG_SET_FIELD    3054 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
REG_SET_FIELD    3076 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    3077 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
REG_SET_FIELD    3079 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
REG_SET_FIELD    3086 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    3088 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    3091 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    3281 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
REG_SET_FIELD    3290 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3292 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3294 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3296 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3299 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3318 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
REG_SET_FIELD    3328 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
REG_SET_FIELD    3330 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
REG_SET_FIELD    3333 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
REG_SET_FIELD    3335 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
REG_SET_FIELD    3336 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
REG_SET_FIELD    3337 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
REG_SET_FIELD    3338 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
REG_SET_FIELD    3356 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3359 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3361 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3363 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3377 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
REG_SET_FIELD    3382 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
REG_SET_FIELD    3926 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    3929 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    3935 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    3943 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4880 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
REG_SET_FIELD    4886 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
REG_SET_FIELD    4933 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
REG_SET_FIELD    4939 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
REG_SET_FIELD    5132 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
REG_SET_FIELD    5137 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
REG_SET_FIELD    5142 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
REG_SET_FIELD    5147 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
REG_SET_FIELD    1307 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
REG_SET_FIELD    1309 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
REG_SET_FIELD    1594 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
REG_SET_FIELD    1596 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
REG_SET_FIELD    1956 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
REG_SET_FIELD    1958 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
REG_SET_FIELD    1960 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
REG_SET_FIELD    1962 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
REG_SET_FIELD    1964 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    1966 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    1968 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    2045 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
REG_SET_FIELD    2046 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
REG_SET_FIELD    2047 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
REG_SET_FIELD    2048 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
REG_SET_FIELD    3059 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
REG_SET_FIELD    4134 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
REG_SET_FIELD    4135 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
REG_SET_FIELD    4136 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
REG_SET_FIELD    4137 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
REG_SET_FIELD    1618 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
REG_SET_FIELD    1644 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
REG_SET_FIELD    1670 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
REG_SET_FIELD    1690 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
REG_SET_FIELD    1691 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
REG_SET_FIELD    1695 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
REG_SET_FIELD    1900 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
REG_SET_FIELD    1903 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
REG_SET_FIELD    1906 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
REG_SET_FIELD    3454 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
REG_SET_FIELD    3456 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
REG_SET_FIELD    3459 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
REG_SET_FIELD    3461 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
REG_SET_FIELD    3464 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
REG_SET_FIELD    3466 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
REG_SET_FIELD    3801 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    3803 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    3805 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
REG_SET_FIELD    3814 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
REG_SET_FIELD    3815 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
REG_SET_FIELD    3816 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
REG_SET_FIELD    3821 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
REG_SET_FIELD    3822 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
REG_SET_FIELD    3823 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
REG_SET_FIELD    3857 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
REG_SET_FIELD    3858 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
REG_SET_FIELD    3859 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
REG_SET_FIELD    3860 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
REG_SET_FIELD    3910 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    3911 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    3912 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    3913 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    4053 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
REG_SET_FIELD    4054 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
REG_SET_FIELD    4055 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
REG_SET_FIELD    4056 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
REG_SET_FIELD    4151 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
REG_SET_FIELD    4152 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
REG_SET_FIELD    4153 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
REG_SET_FIELD    4155 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
REG_SET_FIELD    4156 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
REG_SET_FIELD    4157 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
REG_SET_FIELD    4267 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    4269 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    4271 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    4274 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
REG_SET_FIELD    4282 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
REG_SET_FIELD    4307 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    4308 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
REG_SET_FIELD    4309 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
REG_SET_FIELD    4310 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
REG_SET_FIELD    4312 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
REG_SET_FIELD    4481 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
REG_SET_FIELD    4487 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
REG_SET_FIELD    4500 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
REG_SET_FIELD    4510 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
REG_SET_FIELD    4512 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
REG_SET_FIELD    4515 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
REG_SET_FIELD    4517 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
REG_SET_FIELD    4518 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
REG_SET_FIELD    4519 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
REG_SET_FIELD    4520 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
REG_SET_FIELD    4538 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    4541 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    4543 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    4545 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    4560 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
REG_SET_FIELD    4565 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
REG_SET_FIELD    4566 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
REG_SET_FIELD    4570 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
REG_SET_FIELD    4574 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
REG_SET_FIELD    4991 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4993 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4995 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    5002 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    5008 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
REG_SET_FIELD    5010 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
REG_SET_FIELD    5012 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
REG_SET_FIELD    5014 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
REG_SET_FIELD    5021 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    5024 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    5094 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
REG_SET_FIELD    5095 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
REG_SET_FIELD    5130 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
REG_SET_FIELD    5131 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
REG_SET_FIELD    6290 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
REG_SET_FIELD    6530 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
REG_SET_FIELD    6531 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
REG_SET_FIELD    6532 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
REG_SET_FIELD    6533 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
REG_SET_FIELD    1554 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
REG_SET_FIELD    1555 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
REG_SET_FIELD    1556 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
REG_SET_FIELD    1573 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
REG_SET_FIELD    1574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
REG_SET_FIELD    1603 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
REG_SET_FIELD    1604 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
REG_SET_FIELD    1605 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
REG_SET_FIELD    1622 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
REG_SET_FIELD    1623 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
REG_SET_FIELD    2087 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
REG_SET_FIELD    2089 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
REG_SET_FIELD    2093 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
REG_SET_FIELD    2095 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
REG_SET_FIELD    2101 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
REG_SET_FIELD    2105 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
REG_SET_FIELD    2109 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
REG_SET_FIELD    2113 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
REG_SET_FIELD    2117 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
REG_SET_FIELD    2121 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
REG_SET_FIELD    2383 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
REG_SET_FIELD    2385 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
REG_SET_FIELD    2388 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
REG_SET_FIELD    2390 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
REG_SET_FIELD    2393 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
REG_SET_FIELD    2395 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
REG_SET_FIELD    2519 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
REG_SET_FIELD    2521 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
REG_SET_FIELD    2526 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
REG_SET_FIELD    2528 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
REG_SET_FIELD    2531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
REG_SET_FIELD    2533 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
REG_SET_FIELD    2589 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    2590 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    2591 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    2592 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
REG_SET_FIELD    2828 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2842 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2856 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2869 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2882 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2899 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    2912 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
REG_SET_FIELD    3069 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
REG_SET_FIELD    3070 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
REG_SET_FIELD    3071 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
REG_SET_FIELD    3215 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    3216 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
REG_SET_FIELD    3218 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
REG_SET_FIELD    3245 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    3247 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
REG_SET_FIELD    3250 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
REG_SET_FIELD    3254 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
REG_SET_FIELD    3304 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
REG_SET_FIELD    3305 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
REG_SET_FIELD    3442 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
REG_SET_FIELD    3451 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3453 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3455 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3457 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3460 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3479 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
REG_SET_FIELD    3489 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
REG_SET_FIELD    3491 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
REG_SET_FIELD    3494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
REG_SET_FIELD    3496 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
REG_SET_FIELD    3497 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
REG_SET_FIELD    3498 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
REG_SET_FIELD    3499 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
REG_SET_FIELD    3517 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3520 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3522 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3524 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
REG_SET_FIELD    3538 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
REG_SET_FIELD    3543 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
REG_SET_FIELD    4033 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4035 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4040 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4047 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
REG_SET_FIELD    4330 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
REG_SET_FIELD    4358 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
REG_SET_FIELD    5169 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
REG_SET_FIELD    5472 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
REG_SET_FIELD    5473 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
REG_SET_FIELD    5474 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
REG_SET_FIELD    5475 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
REG_SET_FIELD    5532 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
REG_SET_FIELD    5538 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
REG_SET_FIELD     121 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     122 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     123 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     125 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     127 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
REG_SET_FIELD     128 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     130 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
REG_SET_FIELD     141 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     142 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     144 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
REG_SET_FIELD     146 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
REG_SET_FIELD     147 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     148 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
REG_SET_FIELD     152 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     153 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     158 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
REG_SET_FIELD     159 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
REG_SET_FIELD     162 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
REG_SET_FIELD     163 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
REG_SET_FIELD     169 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     170 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     179 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     180 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     216 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     217 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
REG_SET_FIELD     219 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     221 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     224 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     226 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     228 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     230 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     232 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     234 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     238 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     302 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     303 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     325 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     327 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     329 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     331 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     333 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     337 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     339 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     341 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     343 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     345 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     347 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     350 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     352 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     117 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     118 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     119 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     121 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     123 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
REG_SET_FIELD     124 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     136 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     137 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
REG_SET_FIELD     138 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
REG_SET_FIELD     141 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
REG_SET_FIELD     143 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
REG_SET_FIELD     144 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     145 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
REG_SET_FIELD     149 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     150 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     155 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
REG_SET_FIELD     156 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
REG_SET_FIELD     159 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
REG_SET_FIELD     160 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
REG_SET_FIELD     166 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     167 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     176 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     177 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     205 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     206 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
REG_SET_FIELD     208 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     210 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     212 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     214 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     216 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     218 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     220 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     222 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     226 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
REG_SET_FIELD     290 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     291 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     311 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     313 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     315 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     317 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     319 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     322 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     324 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     326 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     328 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     330 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     332 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     335 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     337 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     208 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
REG_SET_FIELD     210 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
REG_SET_FIELD     211 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
REG_SET_FIELD     212 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
REG_SET_FIELD     213 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
REG_SET_FIELD     214 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
REG_SET_FIELD     215 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
REG_SET_FIELD     216 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
REG_SET_FIELD      86 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 		blackout = REG_SET_FIELD(blackout,
REG_SET_FIELD     101 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
REG_SET_FIELD     104 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
REG_SET_FIELD     105 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
REG_SET_FIELD     416 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     418 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     420 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     422 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     424 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     426 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     447 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     450 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     453 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     456 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD    1018 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    1024 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD     101 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		blackout = REG_SET_FIELD(blackout,
REG_SET_FIELD     115 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
REG_SET_FIELD     118 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
REG_SET_FIELD     119 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
REG_SET_FIELD     281 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
REG_SET_FIELD     286 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
REG_SET_FIELD     306 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
REG_SET_FIELD     499 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     501 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     503 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     505 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     507 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     509 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     530 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     532 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     534 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     536 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     538 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     540 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     542 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     600 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     601 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     602 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     603 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
REG_SET_FIELD     604 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
REG_SET_FIELD     608 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     609 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     610 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
REG_SET_FIELD     611 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
REG_SET_FIELD     612 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
REG_SET_FIELD     613 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     614 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
REG_SET_FIELD     616 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     617 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     622 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
REG_SET_FIELD     623 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
REG_SET_FIELD     624 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
REG_SET_FIELD     634 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     635 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     636 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     664 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     665 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
REG_SET_FIELD     666 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
REG_SET_FIELD     721 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     722 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
REG_SET_FIELD     723 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
REG_SET_FIELD     727 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
REG_SET_FIELD     841 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
REG_SET_FIELD     842 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
REG_SET_FIELD     843 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
REG_SET_FIELD     844 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
REG_SET_FIELD     846 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
REG_SET_FIELD     847 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
REG_SET_FIELD     848 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
REG_SET_FIELD     849 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
REG_SET_FIELD     864 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
REG_SET_FIELD     866 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
REG_SET_FIELD     880 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
REG_SET_FIELD     882 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
REG_SET_FIELD    1163 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    1169 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD     189 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 		blackout = REG_SET_FIELD(blackout,
REG_SET_FIELD     203 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
REG_SET_FIELD     206 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
REG_SET_FIELD     207 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
REG_SET_FIELD     472 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
REG_SET_FIELD     477 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
REG_SET_FIELD     508 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
REG_SET_FIELD     724 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     726 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     728 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     730 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     732 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     734 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     736 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     757 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     759 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     761 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     763 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     765 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     767 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     769 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
REG_SET_FIELD     827 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     828 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     829 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     830 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
REG_SET_FIELD     831 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
REG_SET_FIELD     835 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     836 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     837 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
REG_SET_FIELD     838 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
REG_SET_FIELD     839 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
REG_SET_FIELD     840 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     841 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
REG_SET_FIELD     844 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     845 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     850 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
REG_SET_FIELD     851 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
REG_SET_FIELD     852 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
REG_SET_FIELD     856 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     857 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
REG_SET_FIELD     858 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
REG_SET_FIELD     859 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     860 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
REG_SET_FIELD     861 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
REG_SET_FIELD     862 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     863 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
REG_SET_FIELD     864 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
REG_SET_FIELD     865 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     866 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
REG_SET_FIELD     867 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
REG_SET_FIELD     877 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     878 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     879 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     907 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     908 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
REG_SET_FIELD     909 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     910 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     911 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     912 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     913 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     914 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     915 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
REG_SET_FIELD     916 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
REG_SET_FIELD     965 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     966 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
REG_SET_FIELD     967 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
REG_SET_FIELD     971 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
REG_SET_FIELD    1298 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD    1304 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 			srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD     437 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
REG_SET_FIELD     439 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
REG_SET_FIELD     440 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
REG_SET_FIELD     441 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
REG_SET_FIELD     442 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
REG_SET_FIELD     443 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
REG_SET_FIELD     444 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
REG_SET_FIELD     445 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
REG_SET_FIELD      65 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
REG_SET_FIELD      66 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD      84 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD      85 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
REG_SET_FIELD     121 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     123 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     130 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
REG_SET_FIELD     131 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     132 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     149 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
REG_SET_FIELD     152 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
REG_SET_FIELD     197 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
REG_SET_FIELD     206 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     365 drivers/gpu/drm/amd/amdgpu/iceland_ih.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
REG_SET_FIELD     193 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
REG_SET_FIELD     202 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL,
REG_SET_FIELD     207 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
REG_SET_FIELD     211 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
REG_SET_FIELD     212 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_CNTL,
REG_SET_FIELD     214 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
REG_SET_FIELD     215 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
REG_SET_FIELD     271 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
REG_SET_FIELD     272 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
REG_SET_FIELD     277 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
REG_SET_FIELD     147 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     148 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     149 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     151 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     153 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
REG_SET_FIELD     154 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     156 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
REG_SET_FIELD     170 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     171 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
REG_SET_FIELD     173 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
REG_SET_FIELD     175 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
REG_SET_FIELD     176 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     177 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
REG_SET_FIELD     181 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     182 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     186 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
REG_SET_FIELD     187 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
REG_SET_FIELD     190 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
REG_SET_FIELD     191 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
REG_SET_FIELD     197 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     198 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     207 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     208 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     248 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     249 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
REG_SET_FIELD     251 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     253 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     256 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     258 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     260 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     262 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     264 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     266 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     270 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
REG_SET_FIELD     347 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     348 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     357 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
REG_SET_FIELD     377 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     379 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     381 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     383 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     385 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     389 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     391 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     393 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     395 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     397 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     399 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     402 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     404 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD      91 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
REG_SET_FIELD     103 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
REG_SET_FIELD     104 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
REG_SET_FIELD     105 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     107 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     109 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
REG_SET_FIELD     110 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     122 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
REG_SET_FIELD     123 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
REG_SET_FIELD     124 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
REG_SET_FIELD     127 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
REG_SET_FIELD     129 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
REG_SET_FIELD     130 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
REG_SET_FIELD     131 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
REG_SET_FIELD     136 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
REG_SET_FIELD     141 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
REG_SET_FIELD     142 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
REG_SET_FIELD     145 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
REG_SET_FIELD     146 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
REG_SET_FIELD     152 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     153 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
REG_SET_FIELD     162 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     163 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     194 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     195 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
REG_SET_FIELD     197 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     199 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     202 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     204 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     206 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     208 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     210 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     212 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     216 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
REG_SET_FIELD     280 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
REG_SET_FIELD     281 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     287 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
REG_SET_FIELD     302 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     304 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     306 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     308 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     310 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     313 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     315 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     317 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     319 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     321 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     323 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     326 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     328 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     155 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
REG_SET_FIELD     170 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     172 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     174 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     176 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     178 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     180 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     182 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     196 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     198 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     201 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     203 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     205 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     207 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     214 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
REG_SET_FIELD     216 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
REG_SET_FIELD     223 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
REG_SET_FIELD     224 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
REG_SET_FIELD     227 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
REG_SET_FIELD     228 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
REG_SET_FIELD     235 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
REG_SET_FIELD     237 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
REG_SET_FIELD     250 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
REG_SET_FIELD     251 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
REG_SET_FIELD     289 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     291 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     294 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     296 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     299 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     301 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     303 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     305 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     307 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     309 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     313 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
REG_SET_FIELD     405 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
REG_SET_FIELD     407 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     417 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
REG_SET_FIELD     441 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     444 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     447 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     450 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     453 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     457 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     460 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     463 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     466 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     469 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     472 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
REG_SET_FIELD     476 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     479 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			tmp = REG_SET_FIELD(tmp,
REG_SET_FIELD     140 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
REG_SET_FIELD     305 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
REG_SET_FIELD     358 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
REG_SET_FIELD     324 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
REG_SET_FIELD     346 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
REG_SET_FIELD     357 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
REG_SET_FIELD     504 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
REG_SET_FIELD     534 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 	tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
REG_SET_FIELD      49 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD      50 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
REG_SET_FIELD      66 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD      67 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
REG_SET_FIELD      80 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD      82 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD      84 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD      86 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD      90 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD      92 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
REG_SET_FIELD      93 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
REG_SET_FIELD      94 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
REG_SET_FIELD     128 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
REG_SET_FIELD     134 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 			ih_chicken = REG_SET_FIELD(ih_chicken,
REG_SET_FIELD     154 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     157 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     160 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     169 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
REG_SET_FIELD     174 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
REG_SET_FIELD     224 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
REG_SET_FIELD     238 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     407 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
REG_SET_FIELD     409 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
REG_SET_FIELD     411 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
REG_SET_FIELD     413 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
REG_SET_FIELD     415 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
REG_SET_FIELD      80 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD      83 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD      87 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     102 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     105 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     108 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     127 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
REG_SET_FIELD     129 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		      REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
REG_SET_FIELD     131 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		      REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
REG_SET_FIELD     151 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
REG_SET_FIELD     154 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
REG_SET_FIELD     158 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
REG_SET_FIELD     177 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
REG_SET_FIELD     181 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
REG_SET_FIELD     306 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
REG_SET_FIELD     307 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
REG_SET_FIELD      79 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD      80 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
REG_SET_FIELD      82 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     100 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
REG_SET_FIELD     101 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
REG_SET_FIELD     102 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
REG_SET_FIELD     120 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD     121 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
REG_SET_FIELD     124 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     139 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     141 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     266 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
REG_SET_FIELD     267 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
REG_SET_FIELD     273 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
REG_SET_FIELD      86 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD      87 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
REG_SET_FIELD      89 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     102 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     105 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     108 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     132 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD     133 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     242 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     244 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     117 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD     118 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
REG_SET_FIELD     120 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     139 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     142 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     145 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		doorbell_range = REG_SET_FIELD(doorbell_range,
REG_SET_FIELD     163 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
REG_SET_FIELD     164 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
REG_SET_FIELD     165 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		      REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
REG_SET_FIELD     182 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
REG_SET_FIELD     183 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
REG_SET_FIELD     185 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
REG_SET_FIELD     243 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     245 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     312 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
REG_SET_FIELD     135 drivers/gpu/drm/amd/amdgpu/nv.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
REG_SET_FIELD     136 drivers/gpu/drm/amd/amdgpu/nv.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
REG_SET_FIELD     137 drivers/gpu/drm/amd/amdgpu/nv.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
REG_SET_FIELD     138 drivers/gpu/drm/amd/amdgpu/nv.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
REG_SET_FIELD     765 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
REG_SET_FIELD     767 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
REG_SET_FIELD     773 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     775 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     777 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     779 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     781 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     783 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     785 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     787 drivers/gpu/drm/amd/amdgpu/nv.c 	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
REG_SET_FIELD     793 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     796 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     800 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     803 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     807 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     811 drivers/gpu/drm/amd/amdgpu/nv.c 		hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
REG_SET_FIELD     341 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
REG_SET_FIELD     342 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
REG_SET_FIELD     343 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     354 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
REG_SET_FIELD     355 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     178 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
REG_SET_FIELD     179 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
REG_SET_FIELD     180 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     191 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
REG_SET_FIELD     192 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     270 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
REG_SET_FIELD     271 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
REG_SET_FIELD     272 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     283 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
REG_SET_FIELD     284 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
REG_SET_FIELD     283 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
REG_SET_FIELD     285 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
REG_SET_FIELD     352 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD     355 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
REG_SET_FIELD     395 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD     397 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
REG_SET_FIELD     440 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     442 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
REG_SET_FIELD     443 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
REG_SET_FIELD     460 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     469 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD     473 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
REG_SET_FIELD     475 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
REG_SET_FIELD     972 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD     979 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD    1016 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
REG_SET_FIELD    1021 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
REG_SET_FIELD    1032 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
REG_SET_FIELD    1037 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
REG_SET_FIELD     457 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
REG_SET_FIELD     459 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
REG_SET_FIELD     526 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD     529 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
REG_SET_FIELD     588 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     590 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     599 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     601 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     630 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD     632 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
REG_SET_FIELD     678 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     680 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
REG_SET_FIELD     681 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
REG_SET_FIELD     699 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     707 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
REG_SET_FIELD     709 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
REG_SET_FIELD     711 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
REG_SET_FIELD     726 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
REG_SET_FIELD     730 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
REG_SET_FIELD     737 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD     741 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
REG_SET_FIELD     743 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
REG_SET_FIELD    1350 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
REG_SET_FIELD    1355 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
REG_SET_FIELD    1366 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
REG_SET_FIELD    1371 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
REG_SET_FIELD     821 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD     824 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
REG_SET_FIELD     867 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
REG_SET_FIELD     871 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
REG_SET_FIELD     918 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     952 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
REG_SET_FIELD     965 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     967 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
REG_SET_FIELD     968 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
REG_SET_FIELD    1010 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
REG_SET_FIELD    1024 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
REG_SET_FIELD    1026 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
REG_SET_FIELD    1044 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
REG_SET_FIELD    1050 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD    1054 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
REG_SET_FIELD    1056 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
REG_SET_FIELD    1100 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
REG_SET_FIELD    1114 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
REG_SET_FIELD    1116 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
REG_SET_FIELD    1135 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
REG_SET_FIELD    1141 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD    1145 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
REG_SET_FIELD    1147 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
REG_SET_FIELD    1318 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
REG_SET_FIELD    1324 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD    1993 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
REG_SET_FIELD    2102 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
REG_SET_FIELD     511 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD     514 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
REG_SET_FIELD     573 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
REG_SET_FIELD     608 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
REG_SET_FIELD     643 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     645 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
REG_SET_FIELD     646 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
REG_SET_FIELD     665 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
REG_SET_FIELD     677 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     696 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
REG_SET_FIELD     697 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
REG_SET_FIELD     700 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
REG_SET_FIELD     716 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
REG_SET_FIELD     719 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
REG_SET_FIELD     724 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
REG_SET_FIELD     725 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
REG_SET_FIELD     738 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
REG_SET_FIELD     743 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD     747 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
REG_SET_FIELD     749 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
REG_SET_FIELD    1419 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
REG_SET_FIELD    1354 drivers/gpu/drm/amd/amdgpu/si.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
REG_SET_FIELD    1355 drivers/gpu/drm/amd/amdgpu/si.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
REG_SET_FIELD      57 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
REG_SET_FIELD      84 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
REG_SET_FIELD      85 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
REG_SET_FIELD      86 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
REG_SET_FIELD      87 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
REG_SET_FIELD      89 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
REG_SET_FIELD      90 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
REG_SET_FIELD     263 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
REG_SET_FIELD     265 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
REG_SET_FIELD     270 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
REG_SET_FIELD     273 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
REG_SET_FIELD     349 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
REG_SET_FIELD     352 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
REG_SET_FIELD     354 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
REG_SET_FIELD     359 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
REG_SET_FIELD     405 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
REG_SET_FIELD     409 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
REG_SET_FIELD     290 drivers/gpu/drm/amd/amdgpu/soc15.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
REG_SET_FIELD     291 drivers/gpu/drm/amd/amdgpu/soc15.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
REG_SET_FIELD     292 drivers/gpu/drm/amd/amdgpu/soc15.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
REG_SET_FIELD     293 drivers/gpu/drm/amd/amdgpu/soc15.c 	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
REG_SET_FIELD     848 drivers/gpu/drm/amd/amdgpu/soc15.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
REG_SET_FIELD     849 drivers/gpu/drm/amd/amdgpu/soc15.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
REG_SET_FIELD     895 drivers/gpu/drm/amd/amdgpu/soc15.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
REG_SET_FIELD     897 drivers/gpu/drm/amd/amdgpu/soc15.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
REG_SET_FIELD      64 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD      65 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
REG_SET_FIELD      81 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD      82 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
REG_SET_FIELD     117 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
REG_SET_FIELD     119 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
REG_SET_FIELD     126 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     127 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     129 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
REG_SET_FIELD     130 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
REG_SET_FIELD     133 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
REG_SET_FIELD     147 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
REG_SET_FIELD     149 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
REG_SET_FIELD     152 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
REG_SET_FIELD     199 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
REG_SET_FIELD     208 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     376 drivers/gpu/drm/amd/amdgpu/tonga_ih.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
REG_SET_FIELD      59 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
REG_SET_FIELD      62 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
REG_SET_FIELD      65 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
REG_SET_FIELD      96 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
REG_SET_FIELD     107 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
REG_SET_FIELD     226 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
REG_SET_FIELD     229 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
REG_SET_FIELD     236 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
REG_SET_FIELD     394 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD     395 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD     396 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD     397 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
REG_SET_FIELD     398 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD     399 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD     812 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD     813 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD     814 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD     815 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
REG_SET_FIELD     816 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD     817 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD    1142 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
REG_SET_FIELD     895 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
REG_SET_FIELD     896 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD    1062 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    1063 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD    1064 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD    1065 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
REG_SET_FIELD    1066 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD    1067 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD    1464 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
REG_SET_FIELD     625 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
REG_SET_FIELD     626 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
REG_SET_FIELD     630 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
REG_SET_FIELD     631 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
REG_SET_FIELD     717 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
REG_SET_FIELD     718 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
REG_SET_FIELD     722 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
REG_SET_FIELD     723 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
REG_SET_FIELD     905 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD     906 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD     907 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD     908 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD     909 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD    1078 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    1079 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD    1080 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD    1081 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD    1082 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD    1022 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    1023 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD    1024 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD    1025 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD    1026 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD    1187 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD    1188 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD    1189 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD    1190 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD    1191 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD     848 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
REG_SET_FIELD     849 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
REG_SET_FIELD     850 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
REG_SET_FIELD     851 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
REG_SET_FIELD     852 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
REG_SET_FIELD      51 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
REG_SET_FIELD      52 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
REG_SET_FIELD      65 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
REG_SET_FIELD      81 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
REG_SET_FIELD     107 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
REG_SET_FIELD     108 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
REG_SET_FIELD     126 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
REG_SET_FIELD     146 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
REG_SET_FIELD     170 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     172 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     174 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     176 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
REG_SET_FIELD     180 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     182 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
REG_SET_FIELD     183 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
REG_SET_FIELD     184 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
REG_SET_FIELD     194 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     197 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     201 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
REG_SET_FIELD     240 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
REG_SET_FIELD     242 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1);
REG_SET_FIELD     244 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
REG_SET_FIELD     282 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     284 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
REG_SET_FIELD     332 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
REG_SET_FIELD     337 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
REG_SET_FIELD     398 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
REG_SET_FIELD     420 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
REG_SET_FIELD     363 drivers/gpu/drm/amd/amdgpu/vi.c 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
REG_SET_FIELD     364 drivers/gpu/drm/amd/amdgpu/vi.c 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
REG_SET_FIELD     365 drivers/gpu/drm/amd/amdgpu/vi.c 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
REG_SET_FIELD     366 drivers/gpu/drm/amd/amdgpu/vi.c 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
REG_SET_FIELD     888 drivers/gpu/drm/amd/amdgpu/vi.c 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
REG_SET_FIELD     890 drivers/gpu/drm/amd/amdgpu/vi.c 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
REG_SET_FIELD     966 drivers/gpu/drm/amd/amdgpu/vi.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
REG_SET_FIELD     967 drivers/gpu/drm/amd/amdgpu/vi.c 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
REG_SET_FIELD     892 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
REG_SET_FIELD     893 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
REG_SET_FIELD     899 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
REG_SET_FIELD     900 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
REG_SET_FIELD     906 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
REG_SET_FIELD     907 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
REG_SET_FIELD     913 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
REG_SET_FIELD     914 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
REG_SET_FIELD     920 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
REG_SET_FIELD     921 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
REG_SET_FIELD     143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     167 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     279 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
REG_SET_FIELD     327 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
REG_SET_FIELD     384 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
REG_SET_FIELD     385 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
REG_SET_FIELD     386 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
REG_SET_FIELD     387 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
REG_SET_FIELD     408 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
REG_SET_FIELD     414 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     190 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
REG_SET_FIELD     191 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
REG_SET_FIELD     192 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
REG_SET_FIELD     193 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
REG_SET_FIELD      95 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD      98 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD     161 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 		REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
REG_SET_FIELD     204 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
REG_SET_FIELD    1150 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
REG_SET_FIELD    1151 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
REG_SET_FIELD    1152 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
REG_SET_FIELD    1153 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
REG_SET_FIELD    1154 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
REG_SET_FIELD    1155 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
REG_SET_FIELD    1413 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD    1416 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
REG_SET_FIELD    1445 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
REG_SET_FIELD    1497 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),