REG_SET_4         241 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		value = REG_SET_4(DC_I2C_DATA, 0,
REG_SET_4         110 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_SET_4(AFMT_GENERIC_HDR, 0,
REG_SET_4         500 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
REG_SET_4         222 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
REG_SET_4        1230 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
REG_SET_4        1237 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
REG_SET_4        1244 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
REG_SET_4        1251 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
REG_SET_4        1258 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
REG_SET_4        1265 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
REG_SET_4        1272 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
REG_SET_4        1279 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
REG_SET_4         115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 		REG_SET_4(reg_region_cur, 0,
REG_SET_4         284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
REG_SET_4         569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_4(SCL_TAP_CONTROL, 0,
REG_SET_4         729 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_4(SCL_TAP_CONTROL, 0,
REG_SET_4         550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_SET_4(DCN_EXPANSION_MODE, 0,
REG_SET_4         727 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_SET_4(OTG_TRIGA_CNTL, 0,
REG_SET_4        1135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
REG_SET_4          97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET_4(AFMT_GENERIC_HDR, 0,
REG_SET_4         458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
REG_SET_4         799 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET_4(AFMT_GENERIC_HDR, 0,
REG_SET_4         453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
REG_SET_4         460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
REG_SET_4         467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
REG_SET_4         474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
REG_SET_4         481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
REG_SET_4         488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
REG_SET_4         495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
REG_SET_4         502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
REG_SET_4         509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
REG_SET_4         516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
REG_SET_4         523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
REG_SET_4         530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
REG_SET_4         537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
REG_SET_4         544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
REG_SET_4         551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
REG_SET_4         558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
REG_SET_4         565 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
REG_SET_4         603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
REG_SET_4         610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
REG_SET_4         617 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
REG_SET_4         624 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
REG_SET_4         631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
REG_SET_4         638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
REG_SET_4         645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
REG_SET_4         652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
REG_SET_4         659 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
REG_SET_4         666 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
REG_SET_4         673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
REG_SET_4         680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
REG_SET_4         687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
REG_SET_4         694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
REG_SET_4         701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
REG_SET_4         708 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
REG_SET_4         715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
REG_SET_4         537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_4(DSCC_CONFIG0, 0,
REG_SET_4         549 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
REG_SET_4         618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_4(DSCC_PPS_CONFIG12, 0,
REG_SET_4         624 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_4(DSCC_PPS_CONFIG13, 0,
REG_SET_4         630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_4(DSCC_PPS_CONFIG14, 0,
REG_SET_4         710 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0,
REG_SET_4         706 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 			REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0,
REG_SET_4         198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_SET_4(DCN_EXPANSION_MODE, 0,
REG_SET_4         168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
REG_SET_4         178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
REG_SET_4         188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
REG_SET_4         198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
REG_SET_4         245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_SET_4(AFMT_GENERIC_HDR, 0,
REG_SET_4         124 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	REG_SET_4(DCN_EXPANSION_MODE, 0,