REG_SET_3         262 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
REG_SET_3         267 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
REG_SET_3         285 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
REG_SET_3         124 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_SET_3(DC_I2C_DATA, 0,
REG_SET_3         104 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_SET_3(CUR_COLOR1, 0,
REG_SET_3         109 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_SET_3(CUR_COLOR2, 0,
REG_SET_3         189 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_SET_3(DC_LUT_CONTROL, 0,
REG_SET_3         228 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_SET_3(DEGAMMA_CONTROL, 0,
REG_SET_3         174 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_SET_3(DP_DPHY_SYM0, 0,
REG_SET_3         182 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_SET_3(DP_DPHY_SYM1, 0,
REG_SET_3         210 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET_3(SCL_COEF_RAM_SELECT, 0,
REG_SET_3         322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_SET_3(FORMAT_CONTROL, 0,
REG_SET_3         328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_SET_3(FORMAT_CONTROL, 0,
REG_SET_3         726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET_3(FORMAT_CONTROL, 0,
REG_SET_3         271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
REG_SET_3         553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_3(DSCL_AUTOCAL, 0,
REG_SET_3         684 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_3(DSCL_AUTOCAL, 0,
REG_SET_3         648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
REG_SET_3         653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
REG_SET_3         658 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
REG_SET_3         146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_SET_3(DP_DPHY_SYM0, 0,
REG_SET_3         154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_SET_3(DP_DPHY_SYM1, 0,
REG_SET_3         498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_SET_3(OTG_BLACK_COLOR, 0,
REG_SET_3         682 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_SET_3(OTG_TRIGA_CNTL, 0,
REG_SET_3         691 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_SET_3(OTG_TRIGA_CNTL, 0,
REG_SET_3         555 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_3(DSCC_PPS_CONFIG0, 0,
REG_SET_3         589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_3(DSCC_PPS_CONFIG6, 0,
REG_SET_3         606 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_SET_3(DSCC_PPS_CONFIG10, 0,
REG_SET_3         701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 			REG_SET_3(WBSCL_COEF_RAM_SELECT, 0,
REG_SET_3         149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
REG_SET_3         154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
REG_SET_3         159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
REG_SET_3         649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_SET_3(DMDATA_QOS_CNTL, 0,
REG_SET_3         203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
REG_SET_3         214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
REG_SET_3         225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
REG_SET_3         142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
REG_SET_3         218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
REG_SET_3         269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,