REG_SET_2 227 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_SET_2(AUX_SW_DATA, value, REG_SET_2 71 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, REG_SET_2 76 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, REG_SET_2 248 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c value = REG_SET_2(DC_I2C_DATA, 0, REG_SET_2 256 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_SET_2(DC_I2C_DATA, value, REG_SET_2 57 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(CUR_POSITION, 0, REG_SET_2 61 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(CUR_HOT_SPOT, 0, REG_SET_2 119 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(CUR_SIZE, 0, REG_SET_2 149 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, REG_SET_2 153 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, REG_SET_2 157 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, REG_SET_2 190 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_SET_2(DP_DPHY_SYM2, 0, REG_SET_2 172 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, REG_SET_2 186 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, REG_SET_2 190 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, REG_SET_2 451 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(GRPH_SWAP_CNTL, 0, REG_SET_2 657 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, REG_SET_2 330 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_CNTL, 0, REG_SET_2 338 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_CNTL, 0, REG_SET_2 343 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_CNTL, 0, REG_SET_2 348 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_CNTL, 0, REG_SET_2 354 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_CNTL, 0, REG_SET_2 359 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, REG_SET_2 363 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, REG_SET_2 367 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, REG_SET_2 468 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM1, 0, REG_SET_2 495 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM2, 0, REG_SET_2 512 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM4, 0, REG_SET_2 727 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET_2(DP_MSE_RATE_CNTL, 0, REG_SET_2 131 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(SCL_TAP_CONTROL, 0, REG_SET_2 172 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, REG_SET_2 175 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, REG_SET_2 239 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(VIEWPORT_START, 0, REG_SET_2 243 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(VIEWPORT_SIZE, 0, REG_SET_2 293 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(SCL_HORZ_FILTER_INIT, 0, REG_SET_2 297 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(SCL_VERT_FILTER_INIT, 0, REG_SET_2 331 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(LB_MEMORY_CTRL, 0, REG_SET_2 443 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0, REG_SET_2 447 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0, REG_SET_2 451 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0, REG_SET_2 805 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C11_C12, 0, REG_SET_2 808 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C13_C14, 0, REG_SET_2 811 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C21_C22, 0, REG_SET_2 814 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C23_C24, 0, REG_SET_2 817 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C31_C32, 0, REG_SET_2 820 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(GAMUT_REMAP_C33_C34, 0, REG_SET_2 967 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C11_C12, 0, REG_SET_2 972 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C13_C14, 0, REG_SET_2 977 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C21_C22, 0, REG_SET_2 982 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C23_C24, 0, REG_SET_2 987 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C31_C32, 0, REG_SET_2 992 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(OUTPUT_CSC_C33_C34, 0, REG_SET_2 1214 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, REG_SET_2 1224 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, REG_SET_2 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(cur_csc_reg, 0, REG_SET_2 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_b, 0, REG_SET_2 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_g, 0, REG_SET_2 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_r, 0, REG_SET_2 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_b, 0, REG_SET_2 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_g, 0, REG_SET_2 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_r, 0, REG_SET_2 520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET_2(CM_BNS_VALUES_R, 0, REG_SET_2 524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET_2(CM_BNS_VALUES_G, 0, REG_SET_2 528 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET_2(CM_BNS_VALUES_B, 0, REG_SET_2 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, REG_SET_2 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, REG_SET_2 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(OTG_H_BLANK, 0, REG_SET_2 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(OTG_V_BLANK, 0, REG_SET_2 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(LB_DATA_FORMAT, 0, REG_SET_2 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(LB_MEMORY_CTRL, 0, REG_SET_2 388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_MODE, scl_mode, REG_SET_2 560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_BLACK_OFFSET, 0, REG_SET_2 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_BLACK_OFFSET, 0, REG_SET_2 602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_HORZ_FILTER_INIT, 0, REG_SET_2 608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, REG_SET_2 614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_VERT_FILTER_INIT, 0, REG_SET_2 621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, REG_SET_2 628 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, REG_SET_2 635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, REG_SET_2 650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(RECOUT_START, 0, REG_SET_2 656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(RECOUT_SIZE, 0, REG_SET_2 693 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(MPC_SIZE, 0, REG_SET_2 715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_BLACK_OFFSET, 0, REG_SET_2 720 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET_2(SCL_BLACK_OFFSET, 0, REG_SET_2 584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(BLANK_OFFSET_0, 0, REG_SET_2 594 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DST_AFTER_SCALER, 0, REG_SET_2 619 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(PER_LINE_DELIVERY, 0, REG_SET_2 641 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCN_TTU_QOS_WM, 0, REG_SET_2 686 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(PREFETCH_SETTINS, 0, REG_SET_2 693 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(VBLANK_PARAMETERS_0, 0, REG_SET_2 703 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(PER_LINE_DELIVERY_PRE, 0, REG_SET_2 716 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, REG_SET_2 760 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, REG_SET_2 800 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, REG_SET_2 807 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, REG_SET_2 819 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, REG_SET_2 823 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, REG_SET_2 828 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, REG_SET_2 832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, REG_SET_2 837 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, REG_SET_2 841 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, REG_SET_2 1116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(CURSOR_SETTINS, 0, REG_SET_2 1186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(CURSOR_POSITION, 0, REG_SET_2 1190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET_2(CURSOR_HOT_SPOT, 0, REG_SET_2 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_SET_2(DP_DPHY_SYM2, 0, REG_SET_2 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_VUPDATE_PARAM, 0, REG_SET_2 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, REG_SET_2 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, REG_SET_2 799 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, REG_SET_2 1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, REG_SET_2 1054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, REG_SET_2 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM1, 0, REG_SET_2 454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM2, 0, REG_SET_2 469 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET_2(DP_MSA_TIMING_PARAM4, 0, REG_SET_2 638 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET_2(DP_MSE_RATE_CNTL, 0, REG_SET_2 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, REG_SET_2 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, REG_SET_2 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, REG_SET_2 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_SET_2(FORMAT_CONTROL, 0, REG_SET_2 430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, REG_SET_2 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, REG_SET_2 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, REG_SET_2 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, REG_SET_2 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, REG_SET_2 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, REG_SET_2 580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, REG_SET_2 583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, REG_SET_2 586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, REG_SET_2 590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, REG_SET_2 594 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, REG_SET_2 598 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, REG_SET_2 858 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_3DLUT_DATA, 0, REG_SET_2 862 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_3DLUT_DATA, 0, REG_SET_2 866 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET_2(CM_3DLUT_DATA, 0, REG_SET_2 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCCIF_CONFIG1, 0, REG_SET_2 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG2, 0, REG_SET_2 578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG3, 0, REG_SET_2 585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG5, 0, REG_SET_2 594 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG7, 0, REG_SET_2 598 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG8, 0, REG_SET_2 602 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET_2(DSCC_PPS_CONFIG9, 0, REG_SET_2 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, REG_SET_2 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(BLANK_OFFSET_0, 0, REG_SET_2 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(DST_AFTER_SCALER, 0, REG_SET_2 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(PER_LINE_DELIVERY, 0, REG_SET_2 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(DCN_TTU_QOS_WM, 0, REG_SET_2 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(PREFETCH_SETTINGS, 0, REG_SET_2 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(VBLANK_PARAMETERS_0, 0, REG_SET_2 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(FLIP_PARAMETERS_0, 0, REG_SET_2 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(PER_LINE_DELIVERY_PRE, 0, REG_SET_2 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, REG_SET_2 597 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(CURSOR_SETTINGS, 0, REG_SET_2 1009 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(CURSOR_POSITION, 0, REG_SET_2 1013 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET_2(CURSOR_HOT_SPOT, 0, REG_SET_2 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_DIMENSIONS, 0, REG_SET_2 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_R_CR, 0, REG_SET_2 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_G_Y, 0, REG_SET_2 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_B_CB, 0, REG_SET_2 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_DIMENSIONS, 0, REG_SET_2 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_B_CB, 0, REG_SET_2 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_G_Y, 0, REG_SET_2 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_SET_2(DPG_COLOUR_R_CR, 0, REG_SET_2 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET_2(OTG_GSL_WINDOW_X, 0, REG_SET_2 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET_2(OTG_GSL_WINDOW_Y, 0, REG_SET_2 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET_2(OTG_DSC_START_POSITION, 0, REG_SET_2 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, REG_SET_2 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, REG_SET_2 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, REG_SET_2 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, REG_SET_2 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET_2(CNTL, 0, REG_SET_2 148 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, REG_SET_2 179 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, REG_SET_2 210 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, REG_SET_2 241 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, REG_SET_2 285 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, REG_SET_2 300 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, REG_SET_2 316 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, REG_SET_2 331 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, REG_SET_2 347 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, REG_SET_2 362 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, REG_SET_2 378 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, REG_SET_2 393 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, REG_SET_2 419 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, REG_SET_2 435 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, REG_SET_2 451 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, REG_SET_2 467 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, REG_SET_2 187 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, REG_SET_2 101 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET_2(gpio.MASK_reg, regval,