REG_SET 50 arch/arm/mach-imx/anatop.c REG_SET : REG_CLR; REG_SET 56 arch/arm/mach-imx/anatop.c regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), REG_SET 62 arch/arm/mach-imx/anatop.c regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), REG_SET 68 arch/arm/mach-imx/anatop.c regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), REG_SET 223 drivers/gpu/drm/amd/amdgpu/cikd.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 46 drivers/gpu/drm/amd/amdgpu/nvd.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 1656 drivers/gpu/drm/amd/amdgpu/sid.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 48 drivers/gpu/drm/amd/amdgpu/soc15d.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 105 drivers/gpu/drm/amd/amdgpu/vid.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 64 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, REG_SET 68 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, REG_SET 82 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, REG_SET 231 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_SET(AUX_SW_DATA, value, REG_SET 235 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_SET(AUX_SW_DATA, value, REG_SET 248 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_SET(AUX_SW_DATA, value, REG_SET 129 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, REG_SET 132 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(CUR_SURFACE_ADDRESS, 0, REG_SET 180 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); REG_SET 183 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); REG_SET 195 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DC_LUT_RW_INDEX, 0, REG_SET 199 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, REG_SET 202 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, REG_SET 205 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, REG_SET 212 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); REG_SET 485 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_SET(DP_CONFIG, 0, REG_SET 560 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, REG_SET 413 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_X_START, 0, REG_SET 416 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_Y_START, 0, REG_SET 419 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_X_END, 0, REG_SET 422 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_Y_END, 0, REG_SET 425 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_PITCH, 0, REG_SET 428 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(HW_ROTATION, 0, REG_SET 594 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, REG_SET 631 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, REG_SET 653 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 667 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 671 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 459 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); REG_SET 1350 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); REG_SET 1450 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET(DP_SEC_AUD_N, 0, REG_SET 1454 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, REG_SET 120 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); REG_SET 144 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); REG_SET 199 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); REG_SET 287 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, REG_SET 290 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, REG_SET 358 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_VERT_FILTER_CONTROL, 0, REG_SET 373 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(SCL_HORZ_FILTER_CONTROL, 0, REG_SET 538 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits); REG_SET 744 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode); REG_SET 824 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1); REG_SET 826 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0); REG_SET 1004 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1009 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1016 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1021 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1027 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1033 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1044 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1050 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1056 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1062 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1071 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(OUTPUT_CSC_CONTROL, 0, REG_SET 1218 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, REG_SET 1221 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, REG_SET 1321 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET(REGAMMA_CONTROL, 0, REG_SET 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_b, 0, REG_SET 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_g, 0, REG_SET 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_r, 0, REG_SET 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_b, 0, REG_SET 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_g, 0, REG_SET 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_r, 0, REG_SET 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_SET(CM_GAMUT_REMAP_CONTROL, 0, REG_SET 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); REG_SET 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, REG_SET 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_GAMUT_REMAP_CONTROL, 0, REG_SET 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET( REG_SET 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_TEST_DEBUG_INDEX, 0, REG_SET 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); REG_SET 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_MEM_PWR_CTRL, 0, REG_SET 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET 357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); REG_SET 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); REG_SET 360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); REG_SET 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); REG_SET 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); REG_SET 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0); REG_SET 453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); REG_SET 476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_TEST_DEBUG_INDEX, 0, REG_SET 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_ICSC_CONTROL, 0, REG_SET 597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_MEM_PWR_CTRL, 0, REG_SET 684 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); REG_SET 686 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); REG_SET 687 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); REG_SET 688 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); REG_SET 690 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 692 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 694 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 722 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, REG_SET 733 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); REG_SET 736 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); REG_SET 740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); REG_SET 783 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1); REG_SET 806 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, REG_SET 809 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, REG_SET 812 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, REG_SET 817 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0); REG_SET 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, REG_SET 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, REG_SET 591 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, REG_SET 594 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, REG_SET 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, REG_SET 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, REG_SET 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, REG_SET 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, REG_SET 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, REG_SET 437 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, REG_SET 452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, REG_SET 466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, REG_SET 481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, REG_SET 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, REG_SET 510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, REG_SET 524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, REG_SET 550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, REG_SET 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, REG_SET 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, REG_SET 595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, REG_SET 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, REG_SET 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, REG_SET 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, REG_SET 436 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, REG_SET 440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 444 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 470 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, REG_SET 476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, REG_SET 493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 497 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(BLANK_OFFSET_1, 0, REG_SET 591 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DST_DIMENSIONS, 0, REG_SET 598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(REF_FREQ_TO_PIX_FREQ, 0, REG_SET 602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(VBLANK_PARAMETERS_1, 0, REG_SET 606 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_0, 0, REG_SET 610 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_1, 0, REG_SET 613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_4, 0, REG_SET 616 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_5, 0, REG_SET 623 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(VBLANK_PARAMETERS_2, 0, REG_SET 627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_2, 0, REG_SET 631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_3, 0, REG_SET 634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_6, 0, REG_SET 637 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(NOM_PARAMETERS_7, 0, REG_SET 690 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(PREFETCH_SETTINS_C, 0, REG_SET 697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(VBLANK_PARAMETERS_3, 0, REG_SET 700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(VBLANK_PARAMETERS_4, 0, REG_SET 707 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_SURF0_TTU_CNTL1, 0, REG_SET 710 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_SURF1_TTU_CNTL1, 0, REG_SET 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_CUR0_TTU_CNTL1, 0, REG_SET 763 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, REG_SET 766 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, REG_SET 768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, REG_SET 771 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, REG_SET 773 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, REG_SET 782 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, REG_SET 784 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, REG_SET 788 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, REG_SET 790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, REG_SET 794 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, REG_SET 796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, REG_SET 803 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, REG_SET 1194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_SET(CURSOR_DST_OFFSET, 0, REG_SET 606 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 610 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 660 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 1014 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 1019 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_SET(DP_CONFIG, 0, REG_SET 548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, REG_SET 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_R_CR[mpcc_id], 0, REG_SET 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_G_Y[mpcc_id], 0, REG_SET 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BG_B_CB[mpcc_id], 0, REG_SET 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); REG_SET 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); REG_SET 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); REG_SET 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); REG_SET 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); REG_SET 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, REG_SET 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, REG_SET 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); REG_SET 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); REG_SET 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); REG_SET 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); REG_SET 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); REG_SET 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); REG_SET 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); REG_SET 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); REG_SET 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); REG_SET 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); REG_SET 375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); REG_SET 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); REG_SET 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_SET(FMT_DITHER_RAND_R_SEED, 0, REG_SET 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_SET(FMT_DITHER_RAND_G_SEED, 0, REG_SET 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_SET(FMT_DITHER_RAND_B_SEED, 0, REG_SET 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VSTARTUP_PARAM, 0, REG_SET 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VREADY_PARAM, 0, REG_SET 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_STEREO_CONTROL, 0, REG_SET 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, REG_SET 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, REG_SET 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_H_TOTAL, 0, REG_SET 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL, 0, REG_SET 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MAX, 0, REG_SET 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MIN, 0, REG_SET 596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_GLOBAL_CONTROL0, 0, REG_SET 598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, REG_SET 614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, REG_SET 666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, REG_SET 669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VERT_SYNC_CONTROL, 0, REG_SET 700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, REG_SET 739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_VERT_SYNC_CONTROL, 0, REG_SET 743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, REG_SET 808 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_GLOBAL_CONTROL2, 0, REG_SET 826 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, REG_SET 829 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, REG_SET 855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MID, 0, REG_SET 865 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MAX, 0, REG_SET 868 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MIN, 0, REG_SET 888 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MIN, 0, REG_SET 891 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_V_TOTAL_MAX, 0, REG_SET 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); REG_SET 1291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); REG_SET 1388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET(DP_SEC_AUD_N, 0, REG_SET 1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, REG_SET 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, REG_SET 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); REG_SET 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); REG_SET 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); REG_SET 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); REG_SET 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_DGAM_LUT_DATA, 0, REG_SET 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_MEM_PWR_CTRL, 0, REG_SET 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); REG_SET 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); REG_SET 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); REG_SET 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); REG_SET 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, REG_SET 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, REG_SET 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_LUT_DATA, 0, REG_SET 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, 0); REG_SET 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, REG_SET 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); REG_SET 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); REG_SET 377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); REG_SET 418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); REG_SET 734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); REG_SET 754 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); REG_SET 891 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); REG_SET 905 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); REG_SET 521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET(DSC_DEBUG_CONTROL, 0, REG_SET 543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET(DSCC_CONFIG1, 0, REG_SET 582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_SET(DSCC_PPS_CONFIG4, 0, REG_SET 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_FB_LOCATION_BASE, 0, REG_SET 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_FB_LOCATION_TOP, 0, REG_SET 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_FB_OFFSET, 0, REG_SET 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_AGP_BOT, 0, REG_SET 378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_AGP_TOP, 0, REG_SET 380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_AGP_BASE, 0, REG_SET 383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, REG_SET 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, REG_SET 587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, REG_SET 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, REG_SET 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, REG_SET 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, REG_SET 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(BLANK_OFFSET_1, 0, REG_SET 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DST_DIMENSIONS, 0, REG_SET 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(REF_FREQ_TO_PIX_FREQ, 0, REG_SET 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(VBLANK_PARAMETERS_1, 0, REG_SET 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_0, 0, REG_SET 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_1, 0, REG_SET 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_4, 0, REG_SET 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_5, 0, REG_SET 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(VBLANK_PARAMETERS_2, 0, REG_SET 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_2, 0, REG_SET 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_3, 0, REG_SET 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_6, 0, REG_SET 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(NOM_PARAMETERS_7, 0, REG_SET 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(FLIP_PARAMETERS_1, 0, REG_SET 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(PREFETCH_SETTINGS_C, 0, REG_SET 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(VBLANK_PARAMETERS_3, 0, REG_SET 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(VBLANK_PARAMETERS_4, 0, REG_SET 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(FLIP_PARAMETERS_2, 0, REG_SET 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_SURF0_TTU_CNTL1, 0, REG_SET 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_SURF1_TTU_CNTL1, 0, REG_SET 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_CUR0_TTU_CNTL1, 0, REG_SET 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCN_CUR1_TTU_CNTL1, 0, REG_SET 635 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DMDATA_CNTL, 0, REG_SET 726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 730 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 735 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 739 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 755 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, REG_SET 759 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, REG_SET 763 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 767 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 772 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, REG_SET 776 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, REG_SET 780 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 784 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 810 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, REG_SET 816 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, REG_SET 820 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, REG_SET 825 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 829 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, REG_SET 833 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, REG_SET 837 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, REG_SET 1017 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_SET(CURSOR_DST_OFFSET, 0, REG_SET 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); REG_SET 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); REG_SET 914 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 918 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_SET(DC_IP_REQUEST_CNTL, 0, REG_SET 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); REG_SET 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); REG_SET 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); REG_SET 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); REG_SET 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); REG_SET 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, REG_SET 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); REG_SET 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); REG_SET 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); REG_SET 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg); REG_SET 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, REG_SET 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, REG_SET 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, REG_SET 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); REG_SET 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, REG_SET 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); REG_SET 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); REG_SET 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, REG_SET 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OPTC_BYTES_PER_PIXEL, 0, REG_SET 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OPTC_MEMORY_CONFIG, 0, REG_SET 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OPTC_MEMORY_CONFIG, 0, REG_SET 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); REG_SET 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_GLOBAL_CONTROL0, 0, REG_SET 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_VUPDATE_KEEPOUT, 0, REG_SET 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, REG_SET 340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, REG_SET 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_VUPDATE_KEEPOUT, 0, REG_SET 390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, REG_SET 393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_GLOBAL_CONTROL2, 0, REG_SET 411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_TRIGA_MANUAL_TRIG, 0, REG_SET 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, REG_SET 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, REG_SET 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, REG_SET 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, REG_SET 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, REG_SET 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, REG_SET 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, REG_SET 115 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_FB_LOCATION_BASE, 0, REG_SET 117 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_FB_LOCATION_TOP, 0, REG_SET 119 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_FB_OFFSET, 0, REG_SET 121 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_AGP_BOT, 0, REG_SET 123 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_AGP_TOP, 0, REG_SET 125 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCN_VM_AGP_BASE, 0, REG_SET 162 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, REG_SET 170 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, REG_SET 193 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, REG_SET 201 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, REG_SET 224 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, REG_SET 232 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, REG_SET 255 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, REG_SET 263 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, REG_SET 501 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, REG_SET 80 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(VBLANK_PARAMETERS_5, 0, REG_SET 87 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(VBLANK_PARAMETERS_6, 0, REG_SET 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(FLIP_PARAMETERS_3, 0, REG_SET 97 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(FLIP_PARAMETERS_4, 0, REG_SET 100 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(FLIP_PARAMETERS_5, 0, REG_SET 102 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(FLIP_PARAMETERS_6, 0, REG_SET 181 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, REG_SET 184 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, REG_SET 119 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, REG_SET 128 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, REG_SET 166 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, REG_SET 45 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #ifdef REG_SET REG_SET 384 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f2, v2); } REG_SET 388 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h val = REG_SET(reg, val, f2, v2); \ REG_SET 389 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f3, v3); } REG_SET 128 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); REG_SET 135 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); REG_SET 224 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); REG_SET 149 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); REG_SET 1689 drivers/gpu/drm/radeon/cikd.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 1541 drivers/gpu/drm/radeon/evergreend.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 1155 drivers/gpu/drm/radeon/nid.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 1169 drivers/gpu/drm/radeon/r100.c tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | REG_SET 1170 drivers/gpu/drm/radeon/r100.c REG_SET(RADEON_RB_BLKSZ, rb_blksz) | REG_SET 1171 drivers/gpu/drm/radeon/r100.c REG_SET(RADEON_MAX_FETCH, max_fetch)); REG_SET 1202 drivers/gpu/drm/radeon/r100.c REG_SET(RADEON_INDIRECT2_START, indirect2_start) | REG_SET 1203 drivers/gpu/drm/radeon/r100.c REG_SET(RADEON_INDIRECT1_START, indirect1_start)); REG_SET 60 drivers/gpu/drm/radeon/r100d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ REG_SET 61 drivers/gpu/drm/radeon/r100d.h REG_SET(PACKET0_COUNT, (n))) REG_SET 62 drivers/gpu/drm/radeon/r100d.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 64 drivers/gpu/drm/radeon/r100d.h REG_SET(PACKET3_IT_OPCODE, (op)) | \ REG_SET 65 drivers/gpu/drm/radeon/r100d.h REG_SET(PACKET3_COUNT, (n))) REG_SET 61 drivers/gpu/drm/radeon/r300d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ REG_SET 62 drivers/gpu/drm/radeon/r300d.h REG_SET(PACKET0_COUNT, (n))) REG_SET 63 drivers/gpu/drm/radeon/r300d.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 65 drivers/gpu/drm/radeon/r300d.h REG_SET(PACKET3_IT_OPCODE, (op)) | \ REG_SET 66 drivers/gpu/drm/radeon/r300d.h REG_SET(PACKET3_COUNT, (n))) REG_SET 34 drivers/gpu/drm/radeon/r600d.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 154 drivers/gpu/drm/radeon/rs400.c tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); REG_SET 155 drivers/gpu/drm/radeon/rs400.c tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); REG_SET 201 drivers/gpu/drm/radeon/rv515d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ REG_SET 202 drivers/gpu/drm/radeon/rv515d.h REG_SET(PACKET0_COUNT, (n))) REG_SET 203 drivers/gpu/drm/radeon/rv515d.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 205 drivers/gpu/drm/radeon/rv515d.h REG_SET(PACKET3_IT_OPCODE, (op)) | \ REG_SET 206 drivers/gpu/drm/radeon/rv515d.h REG_SET(PACKET3_COUNT, (n))) REG_SET 1593 drivers/gpu/drm/radeon/sid.h #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) REG_SET 1346 drivers/pinctrl/pinctrl-ingenic.c reg = REG_SET(reg); REG_SET 1357 drivers/pinctrl/pinctrl-ingenic.c reg = REG_SET(reg); REG_SET 1610 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); REG_SET 1619 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); REG_SET 233 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, REG_SET 253 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, REG_SET 278 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->sensor_ctrl + REG_SET, REG_SET 296 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->sensor_ctrl + REG_SET, REG_SET 364 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->sensor_ctrl + REG_SET, REG_SET 374 drivers/thermal/imx_thermal.c regmap_write(map, soc_data->sensor_ctrl + REG_SET, REG_SET 733 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, REG_SET 769 drivers/thermal/imx_thermal.c regmap_write(map, IMX6_MISC0 + REG_SET, REG_SET 771 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->sensor_ctrl + REG_SET, REG_SET 828 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET, REG_SET 837 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->sensor_ctrl + REG_SET, REG_SET 869 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->sensor_ctrl + REG_SET, REG_SET 895 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->sensor_ctrl + REG_SET, REG_SET 915 drivers/thermal/imx_thermal.c regmap_write(map, data->socdata->sensor_ctrl + REG_SET,