REG_READ 168 arch/x86/mm/mmio-mod.c case REG_READ: REG_READ 209 arch/x86/mm/mmio-mod.c case REG_READ: REG_READ 139 arch/x86/mm/pf_in.c CHECK_OP_TYPE(opcode, reg_rop, REG_READ); REG_READ 86 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF; REG_READ 56 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk REG_READ 58 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; REG_READ 63 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider REG_READ 65 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow REG_READ 67 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk REG_READ 69 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; REG_READ 73 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk REG_READ 75 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; REG_READ 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c return REG_READ(MP1_SMN_C2PMSG_83); REG_READ 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000; REG_READ 455 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); REG_READ 460 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); REG_READ 170 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); REG_READ 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); REG_READ 173 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider REG_READ 174 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); REG_READ 176 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); REG_READ 177 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); REG_READ 179 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); REG_READ 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); REG_READ 182 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); REG_READ 183 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); REG_READ 70 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c return REG_READ(MP1_SMN_C2PMSG_83); REG_READ 94 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); REG_READ 98 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c bl_pwm_cntl = REG_READ(BL_PWM_CNTL); REG_READ 237 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c s2 = REG_READ(BIOS_SCRATCH_2); REG_READ 294 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); REG_READ 305 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); REG_READ 344 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_CNTL); REG_READ 346 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_CNTL2); REG_READ 348 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_PERIOD_CNTL); REG_READ 386 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_CNTL); REG_READ 388 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_CNTL2); REG_READ 390 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_READ(BL_PWM_PERIOD_CNTL); REG_READ 400 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c value = REG_READ(BIOS_SCRATCH_2); REG_READ 86 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); REG_READ 78 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value = REG_READ(AUX_ARB_CONTROL); REG_READ 91 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t value = REG_READ(AUX_ARB_CONTROL); REG_READ 99 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_READ(AUX_CONTROL); REG_READ 144 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_READ(AUX_ARB_CONTROL); REG_READ 332 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_READ(AUX_SW_STATUS); REG_READ 994 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clock_hz = REG_READ(PHASE[inst]); REG_READ 111 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c *psr_state = REG_READ(DMCU_IRAM_RD_DATA); REG_READ 336 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); REG_READ 337 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); REG_READ 338 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); REG_READ 339 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | REG_READ 340 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_READ(DMCU_IRAM_RD_DATA)); REG_READ 381 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); REG_READ 408 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); REG_READ 500 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c *psr_state = REG_READ(DMCU_IRAM_RD_DATA); REG_READ 82 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); REG_READ 270 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c value = REG_READ(DP_DPHY_INTERNAL_CTRL); REG_READ 1333 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c value0 = REG_READ(DP_MSE_SAT_UPDATE); REG_READ 102 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c regval = REG_READ(AFMT_VBI_PACKET_CONTROL); REG_READ 345 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c misc1 = REG_READ(DP_MSA_MISC); REG_READ 888 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 914 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 1531 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 198 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c power_ctl = REG_READ(DCFE_MEM_PWR_CTRL); REG_READ 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); REG_READ 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); REG_READ 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); REG_READ 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); REG_READ 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); REG_READ 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); REG_READ 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t scl_mode = REG_READ(SCL_MODE); REG_READ 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); REG_READ 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); REG_READ 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); REG_READ 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); REG_READ 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); REG_READ 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); REG_READ 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); REG_READ 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); REG_READ 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); REG_READ 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); REG_READ 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); REG_READ 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); REG_READ 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); REG_READ 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); REG_READ 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); REG_READ 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); REG_READ 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); REG_READ 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); REG_READ 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); REG_READ 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); REG_READ 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); REG_READ 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); REG_READ 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c value = REG_READ(HUBPREQ_DEBUG_DB); REG_READ 1180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) REG_READ 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); REG_READ 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); REG_READ 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c value = REG_READ(DP_DPHY_INTERNAL_CTRL); REG_READ 1300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c value0 = REG_READ(DP_MSE_SAT_UPDATE); REG_READ 590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c regval = REG_READ(OTG_CONTROL); REG_READ 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c regval = REG_READ(AFMT_VBI_PACKET_CONTROL); REG_READ 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c misc1 = REG_READ(DP_MSA_MISC); REG_READ 751 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 872 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c value = REG_READ(DP_SEC_CNTL); REG_READ 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); REG_READ 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); REG_READ 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); REG_READ 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); REG_READ 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); REG_READ 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); REG_READ 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); REG_READ 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); REG_READ 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); REG_READ 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); REG_READ 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); REG_READ 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); REG_READ 500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); REG_READ 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); REG_READ 503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); REG_READ 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); REG_READ 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); REG_READ 511 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); REG_READ 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); REG_READ 514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); REG_READ 516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); REG_READ 520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); REG_READ 522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); REG_READ 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); REG_READ 525 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); REG_READ 527 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); REG_READ 919 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); REG_READ 1003 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) REG_READ 36 drivers/gpu/drm/gma500/cdv_device.c REG_READ(vga_reg); REG_READ 51 drivers/gpu/drm/gma500/cdv_device.c if (REG_READ(SDVOB) & SDVO_DETECTED) { REG_READ 53 drivers/gpu/drm/gma500/cdv_device.c if (REG_READ(DP_B) & DP_DETECTED) REG_READ 57 drivers/gpu/drm/gma500/cdv_device.c if (REG_READ(SDVOC) & SDVO_DETECTED) { REG_READ 59 drivers/gpu/drm/gma500/cdv_device.c if (REG_READ(DP_C) & DP_DETECTED) REG_READ 75 drivers/gpu/drm/gma500/cdv_device.c return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; REG_READ 80 drivers/gpu/drm/gma500/cdv_device.c u32 max = REG_READ(BLC_PWM_CTL); REG_READ 98 drivers/gpu/drm/gma500/cdv_device.c u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; REG_READ 134 drivers/gpu/drm/gma500/cdv_device.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; REG_READ 265 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); REG_READ 266 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); REG_READ 268 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPARB = REG_READ(DSPARB); REG_READ 269 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); REG_READ 270 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); REG_READ 271 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); REG_READ 272 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); REG_READ 273 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); REG_READ 274 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); REG_READ 276 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveADPA = REG_READ(ADPA); REG_READ 278 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); REG_READ 279 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); REG_READ 280 drivers/gpu/drm/gma500/cdv_device.c regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); REG_READ 281 drivers/gpu/drm/gma500/cdv_device.c regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); REG_READ 282 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveLVDS = REG_READ(LVDS); REG_READ 284 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); REG_READ 286 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); REG_READ 287 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); REG_READ 288 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); REG_READ 290 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); REG_READ 292 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); REG_READ 293 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); REG_READ 325 drivers/gpu/drm/gma500/cdv_device.c temp = REG_READ(DPLL_A); REG_READ 328 drivers/gpu/drm/gma500/cdv_device.c REG_READ(DPLL_A); REG_READ 331 drivers/gpu/drm/gma500/cdv_device.c temp = REG_READ(DPLL_B); REG_READ 334 drivers/gpu/drm/gma500/cdv_device.c REG_READ(DPLL_B); REG_READ 438 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); REG_READ 445 drivers/gpu/drm/gma500/cdv_device.c u32 hotplug = REG_READ(PORT_HOTPLUG_EN); REG_READ 451 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); REG_READ 45 drivers/gpu/drm/gma500/cdv_intel_crt.c temp = REG_READ(reg); REG_READ 108 drivers/gpu/drm/gma500/cdv_intel_crt.c dpll_md = REG_READ(dpll_md_reg); REG_READ 148 drivers/gpu/drm/gma500/cdv_intel_crt.c orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); REG_READ 162 drivers/gpu/drm/gma500/cdv_intel_crt.c if (!(REG_READ(PORT_HOTPLUG_EN) & REG_READ 169 drivers/gpu/drm/gma500/cdv_intel_crt.c if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != REG_READ 133 drivers/gpu/drm/gma500/cdv_intel_display.c ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); REG_READ 145 drivers/gpu/drm/gma500/cdv_intel_display.c ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); REG_READ 151 drivers/gpu/drm/gma500/cdv_intel_display.c *val = REG_READ(SB_DATA); REG_READ 168 drivers/gpu/drm/gma500/cdv_intel_display.c ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); REG_READ 181 drivers/gpu/drm/gma500/cdv_intel_display.c ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); REG_READ 202 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(DPIO_CFG); REG_READ 469 drivers/gpu/drm/gma500/cdv_intel_display.c if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { REG_READ 472 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); REG_READ 473 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(FW_BLC_SELF); REG_READ 481 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(OV_OVADD); REG_READ 497 drivers/gpu/drm/gma500/cdv_intel_display.c fw = REG_READ(DSPFW1); REG_READ 504 drivers/gpu/drm/gma500/cdv_intel_display.c fw = REG_READ(DSPFW2); REG_READ 533 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(FW_BLC_SELF); REG_READ 560 drivers/gpu/drm/gma500/cdv_intel_display.c pfit_control = REG_READ(PFIT_CONTROL); REG_READ 688 drivers/gpu/drm/gma500/cdv_intel_display.c pipeconf = REG_READ(map->conf); REG_READ 708 drivers/gpu/drm/gma500/cdv_intel_display.c if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) REG_READ 727 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(map->dpll); REG_READ 739 drivers/gpu/drm/gma500/cdv_intel_display.c u32 lvds = REG_READ(LVDS); REG_READ 759 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(LVDS); REG_READ 772 drivers/gpu/drm/gma500/cdv_intel_display.c (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); REG_READ 773 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(map->dpll); REG_READ 777 drivers/gpu/drm/gma500/cdv_intel_display.c if (!(REG_READ(map->dpll) & DPLL_LOCK)) { REG_READ 808 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(map->conf); REG_READ 853 drivers/gpu/drm/gma500/cdv_intel_display.c dpll = REG_READ(map->dpll); REG_READ 855 drivers/gpu/drm/gma500/cdv_intel_display.c fp = REG_READ(map->fp0); REG_READ 857 drivers/gpu/drm/gma500/cdv_intel_display.c fp = REG_READ(map->fp1); REG_READ 858 drivers/gpu/drm/gma500/cdv_intel_display.c is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); REG_READ 933 drivers/gpu/drm/gma500/cdv_intel_display.c htot = REG_READ(map->htotal); REG_READ 934 drivers/gpu/drm/gma500/cdv_intel_display.c hsync = REG_READ(map->hsync); REG_READ 935 drivers/gpu/drm/gma500/cdv_intel_display.c vtot = REG_READ(map->vtotal); REG_READ 936 drivers/gpu/drm/gma500/cdv_intel_display.c vsync = REG_READ(map->vsync); REG_READ 391 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 395 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); REG_READ 405 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 409 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); REG_READ 424 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 429 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); REG_READ 431 drivers/gpu/drm/gma500/cdv_intel_dp.c if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { REG_READ 432 drivers/gpu/drm/gma500/cdv_intel_dp.c DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); REG_READ 449 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 462 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); REG_READ 463 drivers/gpu/drm/gma500/cdv_intel_dp.c DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); REG_READ 465 drivers/gpu/drm/gma500/cdv_intel_dp.c if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { REG_READ 486 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 502 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); REG_READ 596 drivers/gpu/drm/gma500/cdv_intel_dp.c if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { REG_READ 598 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(ch_ctl)); REG_READ 620 drivers/gpu/drm/gma500/cdv_intel_dp.c status = REG_READ(ch_ctl); REG_READ 663 drivers/gpu/drm/gma500/cdv_intel_dp.c unpack_aux(REG_READ(ch_data + i), REG_READ 1175 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t dp_reg = REG_READ(intel_dp->output_reg); REG_READ 1395 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(intel_dp->output_reg); REG_READ 1517 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(intel_dp->output_reg); REG_READ 1673 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(intel_dp->output_reg); REG_READ 1685 drivers/gpu/drm/gma500/cdv_intel_dp.c if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) REG_READ 1695 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(intel_dp->output_reg); REG_READ 1700 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(intel_dp->output_reg); REG_READ 1980 drivers/gpu/drm/gma500/cdv_intel_dp.c reg_value = REG_READ(DSPCLK_GATE_D); REG_READ 2070 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_on = REG_READ(PP_CONTROL); REG_READ 2076 drivers/gpu/drm/gma500/cdv_intel_dp.c pwm_ctrl = REG_READ(BLC_PWM_CTL2); REG_READ 2080 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_on = REG_READ(PP_ON_DELAYS); REG_READ 2081 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_off = REG_READ(PP_OFF_DELAYS); REG_READ 2082 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_div = REG_READ(PP_DIVISOR); REG_READ 90 drivers/gpu/drm/gma500/cdv_intel_hdmi.c REG_READ(hdmi_priv->hdmi_reg); REG_READ 100 drivers/gpu/drm/gma500/cdv_intel_hdmi.c hdmib = REG_READ(hdmi_priv->hdmi_reg); REG_READ 106 drivers/gpu/drm/gma500/cdv_intel_hdmi.c REG_READ(hdmi_priv->hdmi_reg); REG_READ 115 drivers/gpu/drm/gma500/cdv_intel_hdmi.c hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg); REG_READ 125 drivers/gpu/drm/gma500/cdv_intel_hdmi.c REG_READ(hdmi_priv->hdmi_reg); REG_READ 62 drivers/gpu/drm/gma500/cdv_intel_lvds.c retval = ((REG_READ(BLC_PWM_CTL) & REG_READ 170 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; REG_READ 196 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | REG_READ 199 drivers/gpu/drm/gma500/cdv_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 207 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & REG_READ 210 drivers/gpu/drm/gma500/cdv_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 317 drivers/gpu/drm/gma500/cdv_intel_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); REG_READ 707 drivers/gpu/drm/gma500/cdv_intel_lvds.c lvds = REG_READ(LVDS); REG_READ 732 drivers/gpu/drm/gma500/cdv_intel_lvds.c pwm = REG_READ(BLC_PWM_CTL2); REG_READ 85 drivers/gpu/drm/gma500/gma_display.c dspcntr = REG_READ(map->cntr); REG_READ 117 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); REG_READ 120 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); REG_READ 122 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->surf); REG_READ 215 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->dpll); REG_READ 218 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 222 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 226 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 232 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->cntr); REG_READ 237 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 243 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->conf); REG_READ 247 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->status); REG_READ 251 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->status); REG_READ 279 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->cntr); REG_READ 284 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 285 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); REG_READ 289 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->conf); REG_READ 292 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->conf); REG_READ 301 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->dpll); REG_READ 304 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 539 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPCNTR = REG_READ(map->cntr); REG_READ 540 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePIPECONF = REG_READ(map->conf); REG_READ 541 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePIPESRC = REG_READ(map->src); REG_READ 542 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveFP0 = REG_READ(map->fp0); REG_READ 543 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveFP1 = REG_READ(map->fp1); REG_READ 544 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDPLL = REG_READ(map->dpll); REG_READ 545 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHTOTAL = REG_READ(map->htotal); REG_READ 546 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHBLANK = REG_READ(map->hblank); REG_READ 547 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHSYNC = REG_READ(map->hsync); REG_READ 548 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVTOTAL = REG_READ(map->vtotal); REG_READ 549 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVBLANK = REG_READ(map->vblank); REG_READ 550 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVSYNC = REG_READ(map->vsync); REG_READ 551 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPSTRIDE = REG_READ(map->stride); REG_READ 554 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPSIZE = REG_READ(map->size); REG_READ 555 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPPOS = REG_READ(map->pos); REG_READ 557 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPBASE = REG_READ(map->base); REG_READ 561 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); REG_READ 585 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 590 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->fp0); REG_READ 593 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->fp1); REG_READ 596 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); REG_READ 710 drivers/gpu/drm/gma500/gma_display.c (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { REG_READ 717 drivers/gpu/drm/gma500/gma_display.c if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == REG_READ 29 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); REG_READ 39 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); REG_READ 51 drivers/gpu/drm/gma500/intel_i2c.c REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | REG_READ 71 drivers/gpu/drm/gma500/intel_i2c.c REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | REG_READ 373 drivers/gpu/drm/gma500/mdfld_device.c temp = REG_READ(mipi_reg); REG_READ 380 drivers/gpu/drm/gma500/mdfld_device.c temp = REG_READ(device_ready_reg); REG_READ 387 drivers/gpu/drm/gma500/mdfld_device.c temp = REG_READ(device_ready_reg); REG_READ 48 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { REG_READ 65 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) REG_READ 82 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & REG_READ 100 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) REG_READ 149 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ REG_READ 153 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ REG_READ 159 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_READ 160 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(dspbase_reg); REG_READ 575 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) REG_READ 585 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) REG_READ 614 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) REG_READ 618 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN) REG_READ 658 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); REG_READ 659 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)); REG_READ 675 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); REG_READ 676 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)); REG_READ 892 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(MIPI_PORT_CONTROL(pipe)); REG_READ 910 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(pipeconf_reg); REG_READ 914 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_READ(dspcntr_reg); REG_READ 77 drivers/gpu/drm/gma500/mdfld_dsi_output.c if ((REG_READ(gen_fifo_stat_reg) & fifo_stat) == fifo_stat) REG_READ 51 drivers/gpu/drm/gma500/mdfld_dsi_output.h REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end)) REG_READ 58 drivers/gpu/drm/gma500/mdfld_dsi_output.h while (FLD_GET(REG_READ(reg), start, end) != val) { REG_READ 90 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if ((mask & REG_READ(gen_fifo_stat_reg)) == mask) REG_READ 94 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg)); REG_READ 188 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if (mask & REG_READ(intr_stat_reg)) REG_READ 203 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c intr_stat = REG_READ(intr_stat_reg); REG_READ 547 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) REG_READ 554 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) { REG_READ 573 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c *(data_out + i) = REG_READ(gen_data_reg); REG_READ 661 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_READ(MIPI_PORT_CONTROL(pipe)); REG_READ 64 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 92 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 106 drivers/gpu/drm/gma500/mdfld_intel_display.c pfit_control = REG_READ(PFIT_CONTROL); REG_READ 124 drivers/gpu/drm/gma500/mdfld_intel_display.c dspcntr = REG_READ(dspcntr_reg); REG_READ 193 drivers/gpu/drm/gma500/mdfld_intel_display.c dspcntr = REG_READ(map->cntr); REG_READ 216 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->linoff); REG_READ 218 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->surf); REG_READ 243 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->cntr); REG_READ 248 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 249 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->base); REG_READ 255 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 260 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->conf); REG_READ 266 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); REG_READ 269 drivers/gpu/drm/gma500/mdfld_intel_display.c !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) REG_READ 273 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 322 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); REG_READ 335 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 340 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 348 drivers/gpu/drm/gma500/mdfld_intel_display.c !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { REG_READ 355 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->cntr); REG_READ 360 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 364 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 375 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->status, REG_READ(map->status)); REG_READ 377 drivers/gpu/drm/gma500/mdfld_intel_display.c if (PIPE_VBLANK_STATUS & REG_READ(map->status)) REG_READ 382 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->cntr); REG_READ 385 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 389 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 395 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(0xb004, REG_READ(0xb004)); REG_READ 398 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->cntr); REG_READ 401 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 405 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 431 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->cntr); REG_READ 436 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); REG_READ 437 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->base); REG_READ 441 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->conf); REG_READ 446 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->conf); REG_READ 452 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); REG_READ 454 drivers/gpu/drm/gma500/mdfld_intel_display.c if ((pipe != 1 && !((REG_READ(PIPEACONF) REG_READ 455 drivers/gpu/drm/gma500/mdfld_intel_display.c | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) REG_READ 459 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 848 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->dspcntr[pipe] = REG_READ(map->cntr); REG_READ 915 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = REG_READ(map->dpll); REG_READ 920 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 986 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); REG_READ 990 drivers/gpu/drm/gma500/mdfld_intel_display.c !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { REG_READ 1001 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->conf); REG_READ 300 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->base), i); REG_READ 335 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); REG_READ 348 drivers/gpu/drm/gma500/oaktrail_crtc.c pfit_control = REG_READ(PFIT_CONTROL); REG_READ 484 drivers/gpu/drm/gma500/oaktrail_crtc.c pipeconf = REG_READ(map->conf); REG_READ 487 drivers/gpu/drm/gma500/oaktrail_crtc.c dspcntr = REG_READ(map->cntr); REG_READ 616 drivers/gpu/drm/gma500/oaktrail_crtc.c dspcntr = REG_READ(map->cntr); REG_READ 641 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->base); REG_READ 643 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->surf); REG_READ 68 drivers/gpu/drm/gma500/oaktrail_device.c max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; REG_READ 84 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); REG_READ 125 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); REG_READ 293 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll = REG_READ(DPLL_CTRL); REG_READ 309 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll = REG_READ(DPLL_CTRL); REG_READ 357 drivers/gpu/drm/gma500/oaktrail_hdmi.c dspcntr = REG_READ(dspcntr_reg); REG_READ 363 drivers/gpu/drm/gma500/oaktrail_hdmi.c pipeconf = REG_READ(pipeconf_reg); REG_READ 367 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(pipeconf_reg); REG_READ 370 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(PCH_PIPEBCONF); REG_READ 393 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(DSPBCNTR); REG_READ 396 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(DSPBCNTR); REG_READ 398 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); REG_READ 399 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(DSPBSURF); REG_READ 403 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(PIPEBCONF); REG_READ 406 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(PIPEBCONF); REG_READ 410 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(PCH_PIPEBCONF); REG_READ 413 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(PCH_PIPEBCONF); REG_READ 420 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(DPLL_CTRL); REG_READ 434 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(DPLL_CTRL); REG_READ 437 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(DPLL_CLK_ENABLE); REG_READ 439 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(DPLL_CLK_ENABLE); REG_READ 445 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(PIPEBCONF); REG_READ 448 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(PIPEBCONF); REG_READ 452 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(PCH_PIPEBCONF); REG_READ 455 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(PCH_PIPEBCONF); REG_READ 461 drivers/gpu/drm/gma500/oaktrail_hdmi.c temp = REG_READ(DSPBCNTR); REG_READ 465 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); REG_READ 466 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_READ(DSPBSURF); REG_READ 44 drivers/gpu/drm/gma500/oaktrail_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | REG_READ 47 drivers/gpu/drm/gma500/oaktrail_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 55 drivers/gpu/drm/gma500/oaktrail_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & REG_READ 58 drivers/gpu/drm/gma500/oaktrail_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 100 drivers/gpu/drm/gma500/oaktrail_lvds.c lvds_port = (REG_READ(LVDS) & REG_READ 162 drivers/gpu/drm/gma500/oaktrail_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); REG_READ 175 drivers/gpu/drm/gma500/oaktrail_lvds.c ret = ((REG_READ(BLC_PWM_CTL) & REG_READ 835 drivers/gpu/drm/gma500/psb_drv.h val = REG_READ(reg); REG_READ 82 drivers/gpu/drm/gma500/psb_intel_display.c pfit_control = REG_READ(PFIT_CONTROL); REG_READ 191 drivers/gpu/drm/gma500/psb_intel_display.c pipeconf = REG_READ(map->conf); REG_READ 215 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); REG_READ 224 drivers/gpu/drm/gma500/psb_intel_display.c u32 lvds = REG_READ(LVDS); REG_READ 245 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(LVDS); REG_READ 250 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); REG_READ 257 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); REG_READ 282 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->conf); REG_READ 311 drivers/gpu/drm/gma500/psb_intel_display.c dpll = REG_READ(map->dpll); REG_READ 313 drivers/gpu/drm/gma500/psb_intel_display.c fp = REG_READ(map->fp0); REG_READ 315 drivers/gpu/drm/gma500/psb_intel_display.c fp = REG_READ(map->fp1); REG_READ 316 drivers/gpu/drm/gma500/psb_intel_display.c is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); REG_READ 388 drivers/gpu/drm/gma500/psb_intel_display.c htot = REG_READ(map->htotal); REG_READ 389 drivers/gpu/drm/gma500/psb_intel_display.c hsync = REG_READ(map->hsync); REG_READ 390 drivers/gpu/drm/gma500/psb_intel_display.c vtot = REG_READ(map->vtotal); REG_READ 391 drivers/gpu/drm/gma500/psb_intel_display.c vsync = REG_READ(map->vsync); REG_READ 64 drivers/gpu/drm/gma500/psb_intel_lvds.c ret = REG_READ(BLC_PWM_CTL); REG_READ 76 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); REG_READ 188 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL); REG_READ 219 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | REG_READ 222 drivers/gpu/drm/gma500/psb_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 230 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & REG_READ 233 drivers/gpu/drm/gma500/psb_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 261 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); REG_READ 262 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); REG_READ 263 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->saveLVDS = REG_READ(LVDS); REG_READ 264 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); REG_READ 265 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePP_CYCLE = REG_READ(PP_CYCLE); REG_READ 267 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); REG_READ 268 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL); REG_READ 269 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); REG_READ 319 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | REG_READ 322 drivers/gpu/drm/gma500/psb_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 325 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & REG_READ 328 drivers/gpu/drm/gma500/psb_intel_lvds.c pp_status = REG_READ(PP_STATUS); REG_READ 433 drivers/gpu/drm/gma500/psb_intel_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); REG_READ 772 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds = REG_READ(LVDS); REG_READ 1076 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); REG_READ 1130 drivers/gpu/drm/gma500/psb_intel_sdvo.c temp = REG_READ(psb_intel_sdvo->sdvo_reg); REG_READ 1143 drivers/gpu/drm/gma500/psb_intel_sdvo.c temp = REG_READ(psb_intel_sdvo->sdvo_reg); REG_READ 1818 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); REG_READ 286 drivers/gpu/drm/gma500/psb_irq.c REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); REG_READ 513 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); REG_READ 572 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); REG_READ 641 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); REG_READ 655 drivers/gpu/drm/gma500/psb_irq.c high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> REG_READ 657 drivers/gpu/drm/gma500/psb_irq.c low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> REG_READ 659 drivers/gpu/drm/gma500/psb_irq.c high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> REG_READ 28 drivers/gpu/drm/gma500/psb_lid.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); REG_READ 30 drivers/gpu/drm/gma500/psb_lid.c pp_status = REG_READ(PP_STATUS); REG_READ 34 drivers/gpu/drm/gma500/psb_lid.c if (REG_READ(PP_STATUS) & PP_ON) { REG_READ 44 drivers/gpu/drm/gma500/psb_lid.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); REG_READ 46 drivers/gpu/drm/gma500/psb_lid.c pp_status = REG_READ(PP_STATUS); REG_READ 41 drivers/input/keyboard/goldfish_events.c type = __raw_readl(edev->addr + REG_READ); REG_READ 42 drivers/input/keyboard/goldfish_events.c code = __raw_readl(edev->addr + REG_READ); REG_READ 43 drivers/input/keyboard/goldfish_events.c value = __raw_readl(edev->addr + REG_READ); REG_READ 29 drivers/media/usb/dvb-usb-v2/ce6230.c case REG_READ: REG_READ 389 drivers/net/wireless/ath/ath9k/ani.c phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); REG_READ 390 drivers/net/wireless/ath/ath9k/ani.c phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); REG_READ 211 drivers/net/wireless/ath/ath9k/ar5008_phy.c txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); REG_READ 442 drivers/net/wireless/ath/ath9k/ar5008_phy.c tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); REG_READ 563 drivers/net/wireless/ath/ath9k/ar5008_phy.c synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; REG_READ 612 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); REG_READ 635 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PCU_MISC_MODE2) & REG_READ 662 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); REG_READ 675 drivers/net/wireless/ath/ath9k/ar5008_phy.c enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & REG_READ 876 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; REG_READ 1122 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); REG_READ 1125 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); REG_READ 1128 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); REG_READ 1134 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); REG_READ 1137 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); REG_READ 1140 drivers/net/wireless/ath/ath9k/ar5008_phy.c nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); REG_READ 1165 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR); REG_READ 1170 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR_LOW); REG_READ 1175 drivers/net/wireless/ath/ath9k/ar5008_phy.c val = REG_READ(ah, AR_PHY_SFCORR_EXT); REG_READ 1227 drivers/net/wireless/ath/ath9k/ar5008_phy.c radar_1 = REG_READ(ah, AR_PHY_RADAR_1); REG_READ 87 drivers/net/wireless/ath/ath9k/ar9002_calib.c if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & REG_READ 122 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ 124 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ 126 drivers/net/wireless/ath/ath9k/ar9002_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); REG_READ 141 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ 143 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ 145 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); REG_READ 147 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); REG_READ 165 drivers/net/wireless/ath/ath9k/ar9002_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ 167 drivers/net/wireless/ath/ath9k/ar9002_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ 169 drivers/net/wireless/ath/ath9k/ar9002_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); REG_READ 171 drivers/net/wireless/ath/ath9k/ar9002_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); REG_READ 299 drivers/net/wireless/ath/ath9k/ar9002_calib.c val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); REG_READ 310 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | REG_READ 354 drivers/net/wireless/ath/ath9k/ar9002_calib.c val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); REG_READ 364 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | REG_READ 373 drivers/net/wireless/ath/ath9k/ar9002_calib.c rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); REG_READ 403 drivers/net/wireless/ath/ath9k/ar9002_calib.c rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); REG_READ 491 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, AR9285_AN_RF2G6); REG_READ 497 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9), REG_READ 556 drivers/net/wireless/ath/ath9k/ar9002_calib.c regList[i][1] = REG_READ(ah, regList[i][0]); REG_READ 558 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x7834); REG_READ 561 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x9808); REG_READ 577 drivers/net/wireless/ath/ath9k/ar9002_calib.c ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); REG_READ 586 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x7834); REG_READ 590 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x7834); REG_READ 592 drivers/net/wireless/ath/ath9k/ar9002_calib.c reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); REG_READ 599 drivers/net/wireless/ath/ath9k/ar9002_calib.c reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); REG_READ 601 drivers/net/wireless/ath/ath9k/ar9002_calib.c offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); REG_READ 602 drivers/net/wireless/ath/ath9k/ar9002_calib.c offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); REG_READ 623 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x7834); REG_READ 626 drivers/net/wireless/ath/ath9k/ar9002_calib.c regVal = REG_READ(ah, 0x9808); REG_READ 666 drivers/net/wireless/ath/ath9k/ar9002_calib.c nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF); REG_READ 772 drivers/net/wireless/ath/ath9k/ar9002_calib.c txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), REG_READ 776 drivers/net/wireless/ath/ath9k/ar9002_calib.c clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & REG_READ 785 drivers/net/wireless/ath/ath9k/ar9002_calib.c reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) REG_READ 787 drivers/net/wireless/ath/ath9k/ar9002_calib.c reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) REG_READ 797 drivers/net/wireless/ath/ath9k/ar9002_calib.c reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5); REG_READ 834 drivers/net/wireless/ath/ath9k/ar9002_calib.c REG_READ(ah, AR_PHY_AGC_CONTROL) | REG_READ 254 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = REG_READ(ah, AR_WA); REG_READ 337 drivers/net/wireless/ath/ath9k/ar9002_hw.c val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; REG_READ 444 drivers/net/wireless/ath/ath9k/ar9002_hw.c val_orig = REG_READ(ah, reg); REG_READ 43 drivers/net/wireless/ath/ath9k/ar9002_mac.c if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { REG_READ 44 drivers/net/wireless/ath/ath9k/ar9002_mac.c if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) REG_READ 46 drivers/net/wireless/ath/ath9k/ar9002_mac.c isr = REG_READ(ah, AR_ISR); REG_READ 50 drivers/net/wireless/ath/ath9k/ar9002_mac.c sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & REG_READ 59 drivers/net/wireless/ath/ath9k/ar9002_mac.c isr = REG_READ(ah, AR_ISR); REG_READ 65 drivers/net/wireless/ath/ath9k/ar9002_mac.c isr2 = REG_READ(ah, AR_ISR_S2); REG_READ 88 drivers/net/wireless/ath/ath9k/ar9002_mac.c isr = REG_READ(ah, AR_ISR_RAC); REG_READ 109 drivers/net/wireless/ath/ath9k/ar9002_mac.c s0_s = REG_READ(ah, AR_ISR_S0_S); REG_READ 110 drivers/net/wireless/ath/ath9k/ar9002_mac.c s1_s = REG_READ(ah, AR_ISR_S1_S); REG_READ 112 drivers/net/wireless/ath/ath9k/ar9002_mac.c s0_s = REG_READ(ah, AR_ISR_S0); REG_READ 114 drivers/net/wireless/ath/ath9k/ar9002_mac.c s1_s = REG_READ(ah, AR_ISR_S1); REG_READ 141 drivers/net/wireless/ath/ath9k/ar9002_mac.c s5_s = REG_READ(ah, AR_ISR_S5_S); REG_READ 143 drivers/net/wireless/ath/ath9k/ar9002_mac.c s5_s = REG_READ(ah, AR_ISR_S5); REG_READ 167 drivers/net/wireless/ath/ath9k/ar9002_mac.c REG_READ(ah, AR_ISR); REG_READ 205 drivers/net/wireless/ath/ath9k/ar9002_mac.c (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); REG_READ 76 drivers/net/wireless/ath/ath9k/ar9002_phy.c reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); REG_READ 98 drivers/net/wireless/ath/ath9k/ar9002_phy.c txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); REG_READ 225 drivers/net/wireless/ath/ath9k/ar9002_phy.c tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); REG_READ 298 drivers/net/wireless/ath/ath9k/ar9002_phy.c MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), REG_READ 336 drivers/net/wireless/ath/ath9k/ar9002_phy.c nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); REG_READ 339 drivers/net/wireless/ath/ath9k/ar9002_phy.c nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); REG_READ 346 drivers/net/wireless/ath/ath9k/ar9002_phy.c nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); REG_READ 349 drivers/net/wireless/ath/ath9k/ar9002_phy.c nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); REG_READ 383 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 400 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 455 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 469 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); REG_READ 248 drivers/net/wireless/ath/ath9k/ar9003_aic.c (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) | REG_READ 251 drivers/net/wireless/ath/ath9k/ar9003_aic.c aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32); REG_READ 443 drivers/net/wireless/ath/ath9k/ar9003_aic.c (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) & REG_READ 468 drivers/net/wireless/ath/ath9k/ar9003_aic.c if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & REG_READ 480 drivers/net/wireless/ath/ath9k/ar9003_aic.c if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & REG_READ 492 drivers/net/wireless/ath/ath9k/ar9003_aic.c value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1); REG_READ 83 drivers/net/wireless/ath/ath9k/ar9003_calib.c if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) REG_READ 183 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ 185 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ 187 drivers/net/wireless/ath/ath9k/ar9003_calib.c (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); REG_READ 271 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, offset_array[i])); REG_READ 288 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, offset_array[i])); REG_READ 293 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, offset_array[i])); REG_READ 306 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); REG_READ 354 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); REG_READ 384 drivers/net/wireless/ath/ath9k/ar9003_calib.c osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; REG_READ 385 drivers/net/wireless/ath/ath9k/ar9003_calib.c osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3; REG_READ 386 drivers/net/wireless/ath/ath9k/ar9003_calib.c osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3; REG_READ 391 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); REG_READ 408 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8))); REG_READ 410 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8))); REG_READ 412 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8))); REG_READ 414 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); REG_READ 418 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); REG_READ 422 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); REG_READ 430 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8))); REG_READ 432 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8))); REG_READ 434 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8))); REG_READ 436 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); REG_READ 440 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); REG_READ 444 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); REG_READ 452 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8))); REG_READ 454 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8))); REG_READ 456 drivers/net/wireless/ath/ath9k/ar9003_calib.c ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8))); REG_READ 458 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); REG_READ 462 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); REG_READ 466 drivers/net/wireless/ath/ath9k/ar9003_calib.c temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); REG_READ 481 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff; REG_READ 502 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff; REG_READ 523 drivers/net/wireless/ath/ath9k/ar9003_calib.c val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff; REG_READ 1092 drivers/net/wireless/ath/ath9k/ar9003_calib.c if (REG_READ(ah, txiqcal_status[i]) & REG_READ 1108 drivers/net/wireless/ath/ath9k/ar9003_calib.c iq_res[idx] = REG_READ(ah, REG_READ 1118 drivers/net/wireless/ath/ath9k/ar9003_calib.c iq_res[idx + 1] = 0xffff & REG_READ(ah, REG_READ 1353 drivers/net/wireless/ath/ath9k/ar9003_calib.c txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & REG_READ 1370 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, CL_TAB_ENTRY(cl_idx[i])); REG_READ 1431 drivers/net/wireless/ath/ath9k/ar9003_calib.c agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL); REG_READ 1481 drivers/net/wireless/ath/ath9k/ar9003_calib.c if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { REG_READ 1482 drivers/net/wireless/ath/ath9k/ar9003_calib.c rx_delay = REG_READ(ah, AR_PHY_RX_DELAY); REG_READ 1493 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_AGC_CONTROL) | REG_READ 1504 drivers/net/wireless/ath/ath9k/ar9003_calib.c if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { REG_READ 1566 drivers/net/wireless/ath/ath9k/ar9003_calib.c REG_READ(ah, AR_PHY_AGC_CONTROL) | REG_READ 3087 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); REG_READ 3093 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c *data = REG_READ(ah, AR9300_OTP_READ_DATA); REG_READ 3729 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 3765 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); REG_READ 3776 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 3806 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); REG_READ 3816 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); REG_READ 3829 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); REG_READ 3942 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c while (pmu_set != REG_READ(ah, pmu_reg)) { REG_READ 3962 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; REG_READ 3990 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) REG_READ 3996 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) REG_READ 4012 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_READ(ah, AR_RTC_REG_CONTROL1) & REG_READ 4017 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_READ(ah, REG_READ 4039 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | REG_READ 5556 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c val = REG_READ(ah, AR_PHY_POWER_TX_SUB); REG_READ 1106 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); REG_READ 1108 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); REG_READ 1110 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); REG_READ 1133 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); REG_READ 1134 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_5 = REG_READ(ah, AR_DMADBG_5); REG_READ 1135 drivers/net/wireless/ath/ath9k/ar9003_hw.c dma_dbg_6 = REG_READ(ah, AR_DMADBG_6); REG_READ 195 drivers/net/wireless/ath/ath9k/ar9003_mac.c async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); REG_READ 198 drivers/net/wireless/ath/ath9k/ar9003_mac.c if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) REG_READ 200 drivers/net/wireless/ath/ath9k/ar9003_mac.c isr = REG_READ(ah, AR_ISR); REG_READ 204 drivers/net/wireless/ath/ath9k/ar9003_mac.c sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; REG_READ 214 drivers/net/wireless/ath/ath9k/ar9003_mac.c isr2 = REG_READ(ah, AR_ISR_S2); REG_READ 240 drivers/net/wireless/ath/ath9k/ar9003_mac.c isr = REG_READ(ah, AR_ISR_RAC); REG_READ 268 drivers/net/wireless/ath/ath9k/ar9003_mac.c s0 = REG_READ(ah, AR_ISR_S0); REG_READ 270 drivers/net/wireless/ath/ath9k/ar9003_mac.c s1 = REG_READ(ah, AR_ISR_S1); REG_READ 282 drivers/net/wireless/ath/ath9k/ar9003_mac.c s5 = REG_READ(ah, AR_ISR_S5_S); REG_READ 284 drivers/net/wireless/ath/ath9k/ar9003_mac.c s5 = REG_READ(ah, AR_ISR_S5); REG_READ 307 drivers/net/wireless/ath/ath9k/ar9003_mac.c (void) REG_READ(ah, AR_ISR); REG_READ 348 drivers/net/wireless/ath/ath9k/ar9003_mac.c (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); REG_READ 39 drivers/net/wireless/ath/ath9k/ar9003_mci.c if (!(REG_READ(ah, address) & bit_position)) { REG_READ 71 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_READ(ah, AR_MCI_INTERRUPT_RAW), REG_READ 72 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); REG_READ 232 drivers/net/wireless/ath/ath9k/ar9003_mci.c saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); REG_READ 236 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); REG_READ 238 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_READ(ah, AR_MCI_INTERRUPT_RAW)); REG_READ 351 drivers/net/wireless/ath/ath9k/ar9003_mci.c intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); REG_READ 375 drivers/net/wireless/ath/ath9k/ar9003_mci.c rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); REG_READ 376 drivers/net/wireless/ath/ath9k/ar9003_mci.c raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); REG_READ 387 drivers/net/wireless/ath/ath9k/ar9003_mci.c mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); REG_READ 929 drivers/net/wireless/ath/ath9k/ar9003_mci.c if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { REG_READ 987 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = REG_READ(ah, AR_MCI_COMMAND2); REG_READ 1177 drivers/net/wireless/ath/ath9k/ar9003_mci.c saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); REG_READ 1178 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = REG_READ(ah, AR_BTCOEX_CTRL); REG_READ 1299 drivers/net/wireless/ath/ath9k/ar9003_mci.c value = REG_READ(ah, AR_BTCOEX_CTRL); REG_READ 1307 drivers/net/wireless/ath/ath9k/ar9003_mci.c value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); REG_READ 1315 drivers/net/wireless/ath/ath9k/ar9003_mci.c value = MS(REG_READ(ah, AR_MCI_RX_STATUS), REG_READ 1321 drivers/net/wireless/ath/ath9k/ar9003_mci.c value = MS(REG_READ(ah, AR_MCI_RX_STATUS), REG_READ 1341 drivers/net/wireless/ath/ath9k/ar9003_mci.c if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) & REG_READ 1430 drivers/net/wireless/ath/ath9k/ar9003_mci.c btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2); REG_READ 1438 drivers/net/wireless/ath/ath9k/ar9003_mci.c diag_sw = REG_READ(ah, AR_DIAG_SW); REG_READ 1444 drivers/net/wireless/ath/ath9k/ar9003_mci.c lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3; REG_READ 1445 drivers/net/wireless/ath/ath9k/ar9003_mci.c bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP); REG_READ 1466 drivers/net/wireless/ath/ath9k/ar9003_mci.c offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); REG_READ 1493 drivers/net/wireless/ath/ath9k/ar9003_mci.c gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); REG_READ 299 drivers/net/wireless/ath/ath9k/ar9003_paprd.c entry[i] = REG_READ(ah, reg); REG_READ 940 drivers/net/wireless/ath/ath9k/ar9003_paprd.c data_L[i] = REG_READ(ah, reg + (i << 2)); REG_READ 946 drivers/net/wireless/ath/ath9k/ar9003_paprd.c data_U[i] = REG_READ(ah, reg + (i << 2)); REG_READ 626 drivers/net/wireless/ath/ath9k/ar9003_phy.c (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); REG_READ 644 drivers/net/wireless/ath/ath9k/ar9003_phy.c phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); REG_READ 669 drivers/net/wireless/ath/ath9k/ar9003_phy.c synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; REG_READ 712 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); REG_READ 730 drivers/net/wireless/ath/ath9k/ar9003_phy.c if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) REG_READ 1067 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; REG_READ 1361 drivers/net/wireless/ath/ath9k/ar9003_phy.c nf = MS(REG_READ(ah, ah->nf_regs[i]), REG_READ 1368 drivers/net/wireless/ath/ath9k/ar9003_phy.c nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), REG_READ 1418 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR); REG_READ 1423 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR_LOW); REG_READ 1428 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_SFCORR_EXT); REG_READ 1471 drivers/net/wireless/ath/ath9k/ar9003_phy.c radar_1 = REG_READ(ah, AR_PHY_RADAR_1); REG_READ 1512 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 1544 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 1592 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 1601 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 1612 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); REG_READ 1621 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 1660 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); REG_READ 2016 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RADAR_0); REG_READ 2021 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RADAR_0); REG_READ 2056 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & REG_READ 2062 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & REG_READ 2071 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; REG_READ 2112 drivers/net/wireless/ath/ath9k/ar9003_phy.c ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); REG_READ 2146 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), REG_READ 2147 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); REG_READ 2149 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_READ(ah, AR_PHY_GEN_CTRL)); REG_READ 2175 drivers/net/wireless/ath/ath9k/ar9003_phy.c val = REG_READ(ah, AR_PHY_RESTART); REG_READ 162 drivers/net/wireless/ath/ath9k/ar9003_rtt.c val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)), REG_READ 48 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); REG_READ 53 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) REG_READ 56 drivers/net/wireless/ath/ath9k/ar9003_wow.c if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & REG_READ 192 drivers/net/wireless/ath/ath9k/ar9003_wow.c rval = REG_READ(ah, AR_WOW_PATTERN); REG_READ 213 drivers/net/wireless/ath/ath9k/ar9003_wow.c rval = REG_READ(ah, AR_MAC_PCU_WOW4); REG_READ 236 drivers/net/wireless/ath/ath9k/ar9003_wow.c AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); REG_READ 238 drivers/net/wireless/ath/ath9k/ar9003_wow.c AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); REG_READ 256 drivers/net/wireless/ath/ath9k/ar9003_wow.c u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); REG_READ 281 drivers/net/wireless/ath/ath9k/ar9003_wow.c wa_reg = REG_READ(ah, AR_WA); REG_READ 364 drivers/net/wireless/ath/ath9k/ar9003_wow.c keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); REG_READ 395 drivers/net/wireless/ath/ath9k/ar9003_wow.c magic_pattern = REG_READ(ah, AR_WOW_PATTERN); REG_READ 417 drivers/net/wireless/ath/ath9k/ar9003_wow.c host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL); REG_READ 349 drivers/net/wireless/ath/ath9k/btcoex.c val = REG_READ(ah, 0x50040); REG_READ 250 drivers/net/wireless/ath/ath9k/calib.c u32 bb_agc_ctl = REG_READ(ah, AR_PHY_AGC_CONTROL); REG_READ 308 drivers/net/wireless/ath/ath9k/calib.c if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & REG_READ 341 drivers/net/wireless/ath/ath9k/calib.c REG_READ(ah, AR_PHY_AGC_CONTROL)); REG_READ 409 drivers/net/wireless/ath/ath9k/calib.c if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { REG_READ 477 drivers/net/wireless/ath/ath9k/calib.c else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) REG_READ 582 drivers/net/wireless/ath/ath9k/channel.c sc->sched.next_tbtt = REG_READ(ah, AR_NEXT_TBTT_TIMER); REG_READ 947 drivers/net/wireless/ath/ath9k/debug.c "0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2)); REG_READ 304 drivers/net/wireless/ath/ath9k/eeprom_4k.c pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), REG_READ 782 drivers/net/wireless/ath/ath9k/eeprom_4k.c regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 798 drivers/net/wireless/ath/ath9k/eeprom_4k.c regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 799 drivers/net/wireless/ath/ath9k/eeprom_4k.c regVal = REG_READ(ah, AR_PHY_CCK_DETECT); REG_READ 805 drivers/net/wireless/ath/ath9k/eeprom_4k.c regVal = REG_READ(ah, AR_PHY_CCK_DETECT); REG_READ 812 drivers/net/wireless/ath/ath9k/eeprom_4k.c regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); REG_READ 320 drivers/net/wireless/ath/ath9k/eeprom_9287.c tmpVal = REG_READ(ah, 0xa270); REG_READ 327 drivers/net/wireless/ath/ath9k/eeprom_9287.c tmpVal = REG_READ(ah, 0xb270); REG_READ 335 drivers/net/wireless/ath/ath9k/eeprom_9287.c tmpVal = REG_READ(ah, 0xa398); REG_READ 345 drivers/net/wireless/ath/ath9k/eeprom_9287.c tmpVal = REG_READ(ah, 0xb398); REG_READ 374 drivers/net/wireless/ath/ath9k/eeprom_9287.c pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), REG_READ 870 drivers/net/wireless/ath/ath9k/eeprom_9287.c (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) REG_READ 919 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); REG_READ 935 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); REG_READ 496 drivers/net/wireless/ath/ath9k/eeprom_def.c (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & REG_READ 791 drivers/net/wireless/ath/ath9k/eeprom_def.c pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), REG_READ 498 drivers/net/wireless/ath/ath9k/htc_drv_init.c val = REG_READ(ah, reg_offset); REG_READ 523 drivers/net/wireless/ath/ath9k/htc_drv_init.c (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); REG_READ 532 drivers/net/wireless/ath/ath9k/htc_drv_init.c *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), REG_READ 84 drivers/net/wireless/ath/ath9k/hw.c if ((REG_READ(ah, reg) & mask) == val) REG_READ 92 drivers/net/wireless/ath/ath9k/hw.c timeout, reg, REG_READ(ah, reg), mask, val); REG_READ 270 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_SREV); REG_READ 288 drivers/net/wireless/ath/ath9k/hw.c srev = REG_READ(ah, AR_SREV); REG_READ 365 drivers/net/wireless/ath/ath9k/hw.c regHold[i] = REG_READ(ah, addr); REG_READ 369 drivers/net/wireless/ath/ath9k/hw.c rdData = REG_READ(ah, addr); REG_READ 380 drivers/net/wireless/ath/ath9k/hw.c rdData = REG_READ(ah, addr); REG_READ 610 drivers/net/wireless/ath/ath9k/hw.c ah->WARegVal = REG_READ(ah, AR_WA); REG_READ 641 drivers/net/wireless/ath/ath9k/hw.c ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); REG_READ 745 drivers/net/wireless/ath/ath9k/hw.c while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { REG_READ 757 drivers/net/wireless/ath/ath9k/hw.c return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; REG_READ 867 drivers/net/wireless/ath/ath9k/hw.c regval = REG_READ(ah, AR_PHY_PLL_MODE); REG_READ 879 drivers/net/wireless/ath/ath9k/hw.c regval = REG_READ(ah, AR_PHY_PLL_MODE); REG_READ 905 drivers/net/wireless/ath/ath9k/hw.c REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); REG_READ 908 drivers/net/wireless/ath/ath9k/hw.c REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); REG_READ 981 drivers/net/wireless/ath/ath9k/hw.c ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); REG_READ 987 drivers/net/wireless/ath/ath9k/hw.c REG_READ(ah, AR_INTCFG), msi_cfg); REG_READ 1105 drivers/net/wireless/ath/ath9k/hw.c eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ REG_READ 1107 drivers/net/wireless/ath/ath9k/hw.c reg = REG_READ(ah, AR_USEC); REG_READ 1359 drivers/net/wireless/ath/ath9k/hw.c (void)REG_READ(ah, AR_RTC_DERIVED_CLK); REG_READ 1376 drivers/net/wireless/ath/ath9k/hw.c tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); REG_READ 1524 drivers/net/wireless/ath/ath9k/hw.c } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || REG_READ 1525 drivers/net/wireless/ath/ath9k/hw.c (REG_READ(ah, AR_CR) & AR_CR_RXE)) REG_READ 1634 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_NAV); REG_READ 1648 drivers/net/wireless/ath/ath9k/hw.c if (REG_READ(ah, AR_CFG) == 0xdeadbeef) REG_READ 1657 drivers/net/wireless/ath/ath9k/hw.c last_val = REG_READ(ah, AR_OBS_BUS_1); REG_READ 1659 drivers/net/wireless/ath/ath9k/hw.c reg = REG_READ(ah, AR_OBS_BUS_1); REG_READ 1756 drivers/net/wireless/ath/ath9k/hw.c mask = REG_READ(ah, AR_CFG); REG_READ 1764 drivers/net/wireless/ath/ath9k/hw.c REG_READ(ah, AR_CFG)); REG_READ 1915 drivers/net/wireless/ath/ath9k/hw.c saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); REG_READ 1919 drivers/net/wireless/ath/ath9k/hw.c macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; REG_READ 1925 drivers/net/wireless/ath/ath9k/hw.c saveLedState = REG_READ(ah, AR_CFG_LED) & REG_READ 2190 drivers/net/wireless/ath/ath9k/hw.c if ((REG_READ(ah, AR_RTC_STATUS) & REG_READ 2210 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; REG_READ 2631 drivers/net/wireless/ath/ath9k/hw.c ah->ent_mode = REG_READ(ah, AR_ENT_OTP); REG_READ 2720 drivers/net/wireless/ath/ath9k/hw.c tmp = REG_READ(ah, addr); REG_READ 2816 drivers/net/wireless/ath/ath9k/hw.c (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) REG_READ 2830 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); REG_READ 2832 drivers/net/wireless/ath/ath9k/hw.c val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); REG_READ 2879 drivers/net/wireless/ath/ath9k/hw.c u32 bits = REG_READ(ah, AR_RX_FILTER); REG_READ 2880 drivers/net/wireless/ath/ath9k/hw.c u32 phybits = REG_READ(ah, AR_PHY_ERR); REG_READ 3023 drivers/net/wireless/ath/ath9k/hw.c tsf_upper1 = REG_READ(ah, AR_TSF_U32); REG_READ 3025 drivers/net/wireless/ath/ath9k/hw.c tsf_lower = REG_READ(ah, AR_TSF_L32); REG_READ 3026 drivers/net/wireless/ath/ath9k/hw.c tsf_upper2 = REG_READ(ah, AR_TSF_U32); REG_READ 3110 drivers/net/wireless/ath/ath9k/hw.c return REG_READ(ah, AR_TSF_L32); REG_READ 126 drivers/net/wireless/ath/ath9k/hw.h (((REG_READ(_a, _r) & _f) >> _f##_S)) REG_READ 48 drivers/net/wireless/ath/ath9k/mac.c return REG_READ(ah, AR_QTXDP(q)); REG_READ 69 drivers/net/wireless/ath/ath9k/mac.c npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; REG_READ 72 drivers/net/wireless/ath/ath9k/mac.c if (REG_READ(ah, AR_Q_TXE) & (1 << q)) REG_READ 114 drivers/net/wireless/ath/ath9k/mac.c txcfg = REG_READ(ah, AR_TXCFG); REG_READ 653 drivers/net/wireless/ath/ath9k/mac.c reg = REG_READ(ah, AR_OBS_BUS_1); REG_READ 710 drivers/net/wireless/ath/ath9k/mac.c if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) REG_READ 714 drivers/net/wireless/ath/ath9k/mac.c mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; REG_READ 730 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_CR), REG_READ 731 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_DIAG_SW), REG_READ 732 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_DMADBG_7)); REG_READ 765 drivers/net/wireless/ath/ath9k/mac.c host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); REG_READ 772 drivers/net/wireless/ath/ath9k/mac.c host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); REG_READ 787 drivers/net/wireless/ath/ath9k/mac.c (void) REG_READ(ah, AR_IER); REG_READ 790 drivers/net/wireless/ath/ath9k/mac.c (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); REG_READ 793 drivers/net/wireless/ath/ath9k/mac.c (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); REG_READ 834 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); REG_READ 848 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE), REG_READ 849 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_INTR_PRIO_ASYNC_MASK)); REG_READ 852 drivers/net/wireless/ath/ath9k/mac.c ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); REG_READ 863 drivers/net/wireless/ath/ath9k/mac.c _msi_reg = REG_READ(ah, AR_PCIE_MSI); REG_READ 922 drivers/net/wireless/ath/ath9k/mac.c REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE); REG_READ 941 drivers/net/wireless/ath/ath9k/reg.h ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) REG_READ 42 drivers/net/wireless/ath/ath9k/rng.c v1 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; REG_READ 43 drivers/net/wireless/ath/ath9k/rng.c v2 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; REG_READ 124 drivers/net/wireless/ath/hw.c id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; REG_READ 151 drivers/net/wireless/ath/hw.c cycles = REG_READ(ah, AR_CCCNT); REG_READ 152 drivers/net/wireless/ath/hw.c busy = REG_READ(ah, AR_RCCNT); REG_READ 153 drivers/net/wireless/ath/hw.c rx = REG_READ(ah, AR_RFCNT); REG_READ 154 drivers/net/wireless/ath/hw.c tx = REG_READ(ah, AR_TFCNT); REG_READ 53 drivers/net/wireless/ath/key.c keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); REG_READ 136 drivers/net/wireless/st/cw1200/fwio.c REG_READ(ST90TDS_CONFIG_REG_ID, val32);