REG_OFS            82 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CR	(0x84 + REG_OFS)/* L1 Control */
REG_OFS            83 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1WHPCR	(0x88 + REG_OFS)/* L1 Window Hor Position Config */
REG_OFS            84 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1WVPCR	(0x8C + REG_OFS)/* L1 Window Vert Position Config */
REG_OFS            85 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CKCR	(0x90 + REG_OFS)/* L1 Color Keying Configuration */
REG_OFS            86 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1PFCR	(0x94 + REG_OFS)/* L1 Pixel Format Configuration */
REG_OFS            87 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CACR	(0x98 + REG_OFS)/* L1 Constant Alpha Config */
REG_OFS            88 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1DCCR	(0x9C + REG_OFS)/* L1 Default Color Configuration */
REG_OFS            89 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1BFCR	(0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
REG_OFS            90 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1FBBCR	(0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
REG_OFS            91 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1AFBCR	(0xA8 + REG_OFS)/* L1 AuxFB Control */
REG_OFS            92 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CFBAR	(0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
REG_OFS            93 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CFBLR	(0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
REG_OFS            94 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CFBLNR	(0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
REG_OFS            95 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1AFBAR	(0xB8 + REG_OFS)/* L1 AuxFB Address */
REG_OFS            96 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1AFBLR	(0xBC + REG_OFS)/* L1 AuxFB Length */
REG_OFS            97 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1AFBLNR	(0xC0 + REG_OFS)/* L1 AuxFB Line Number */
REG_OFS            98 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1CLUTWR	(0xC4 + REG_OFS)/* L1 CLUT Write */
REG_OFS            99 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1YS1R	(0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
REG_OFS           100 drivers/gpu/drm/stm/ltdc.c #define LTDC_L1YS2R	(0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */