REG_OFFSET         26 arch/arm/kvm/emulate.c #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
REG_OFFSET         43 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[0]), /* r8 */
REG_OFFSET         44 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[1]), /* r9 */
REG_OFFSET         45 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[2]), /* r10 */
REG_OFFSET         46 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[3]), /* r11 */
REG_OFFSET         47 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[4]), /* r12 */
REG_OFFSET         48 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[5]), /* r13 */
REG_OFFSET         49 arch/arm/kvm/emulate.c 		REG_OFFSET(fiq_regs[6]), /* r14 */
REG_OFFSET         59 arch/arm/kvm/emulate.c 		REG_OFFSET(irq_regs[0]), /* r13 */
REG_OFFSET         60 arch/arm/kvm/emulate.c 		REG_OFFSET(irq_regs[1]), /* r14 */
REG_OFFSET         70 arch/arm/kvm/emulate.c 		REG_OFFSET(svc_regs[0]), /* r13 */
REG_OFFSET         71 arch/arm/kvm/emulate.c 		REG_OFFSET(svc_regs[1]), /* r14 */
REG_OFFSET         81 arch/arm/kvm/emulate.c 		REG_OFFSET(abt_regs[0]), /* r13 */
REG_OFFSET         82 arch/arm/kvm/emulate.c 		REG_OFFSET(abt_regs[1]), /* r14 */
REG_OFFSET         92 arch/arm/kvm/emulate.c 		REG_OFFSET(und_regs[0]), /* r13 */
REG_OFFSET         93 arch/arm/kvm/emulate.c 		REG_OFFSET(und_regs[1]), /* r14 */
REG_OFFSET         89 arch/arm/mach-ixp4xx/avila-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET         98 arch/arm/mach-ixp4xx/avila-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET         67 arch/arm/mach-ixp4xx/coyote-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        104 arch/arm/mach-ixp4xx/coyote-setup.c 			(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
REG_OFFSET        137 arch/arm/mach-ixp4xx/dsmg600-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET        146 arch/arm/mach-ixp4xx/dsmg600-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        100 arch/arm/mach-ixp4xx/fsg-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET        109 arch/arm/mach-ixp4xx/fsg-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET         61 arch/arm/mach-ixp4xx/gateway7001-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        245 arch/arm/mach-ixp4xx/goramo_mlr.c 			REG_OFFSET,
REG_OFFSET        255 arch/arm/mach-ixp4xx/goramo_mlr.c 			REG_OFFSET,
REG_OFFSET         98 arch/arm/mach-ixp4xx/gtwx5715-setup.c 	.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        162 arch/arm/mach-ixp4xx/ixdp425-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET        171 arch/arm/mach-ixp4xx/ixdp425-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        140 arch/arm/mach-ixp4xx/nas100d-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET        149 arch/arm/mach-ixp4xx/nas100d-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        160 arch/arm/mach-ixp4xx/nslu2-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET        169 arch/arm/mach-ixp4xx/nslu2-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        127 arch/arm/mach-ixp4xx/omixp-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET        135 arch/arm/mach-ixp4xx/omixp-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET         84 arch/arm/mach-ixp4xx/vulcan-setup.c 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
REG_OFFSET         93 arch/arm/mach-ixp4xx/vulcan-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET         62 arch/arm/mach-ixp4xx/wg302v2-setup.c 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
REG_OFFSET         20 arch/arm64/kvm/regmap.c #define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
REG_OFFSET         30 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         38 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_r8_fiq),  /* r8 */
REG_OFFSET         39 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_r9_fiq),  /* r9 */
REG_OFFSET         40 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_r10_fiq), /* r10 */
REG_OFFSET         41 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_r11_fiq), /* r11 */
REG_OFFSET         42 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_r12_fiq), /* r12 */
REG_OFFSET         43 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_sp_fiq),  /* r13 */
REG_OFFSET         44 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_lr_fiq),  /* r14 */
REG_OFFSET         45 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         55 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_sp_irq), /* r13 */
REG_OFFSET         56 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_lr_irq), /* r14 */
REG_OFFSET         57 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         67 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_sp_svc), /* r13 */
REG_OFFSET         68 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_lr_svc), /* r14 */
REG_OFFSET         69 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         79 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_sp_abt), /* r13 */
REG_OFFSET         80 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_lr_abt), /* r14 */
REG_OFFSET         81 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         91 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_sp_und), /* r13 */
REG_OFFSET         92 arch/arm64/kvm/regmap.c 		REG_OFFSET(compat_lr_und), /* r14 */
REG_OFFSET         93 arch/arm64/kvm/regmap.c 		REG_OFFSET(pc)
REG_OFFSET         22 arch/mips/ar7/irq.c #define CR_OFFSET(irq)		(REG_OFFSET(irq, 1))	/* 0x10 */
REG_OFFSET         24 arch/mips/ar7/irq.c #define ESR_OFFSET(irq)		(REG_OFFSET(irq, 2))	/* 0x20 */
REG_OFFSET         26 arch/mips/ar7/irq.c #define ECR_OFFSET(irq)		(REG_OFFSET(irq, 3))	/* 0x30 */
REG_OFFSET         30 arch/mips/ar7/irq.c #define PM_OFFSET(irq)		(REG_OFFSET(irq, 5))	/* 0x50 */
REG_OFFSET         31 arch/mips/ar7/irq.c #define TM_OFFSET(irq)		(REG_OFFSET(irq, 6))	/* 0x60 */
REG_OFFSET         89 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DEVICE_READY_REG(pipe)		(0xb000 + REG_OFFSET(pipe))
REG_OFFSET         90 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_INTR_STAT_REG(pipe)		(0xb004 + REG_OFFSET(pipe))
REG_OFFSET         91 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_INTR_EN_REG(pipe)			(0xb008 + REG_OFFSET(pipe))
REG_OFFSET         92 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DSI_FUNC_PRG_REG(pipe)		(0xb00c + REG_OFFSET(pipe))
REG_OFFSET         93 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HS_TX_TIMEOUT_REG(pipe)		(0xb010 + REG_OFFSET(pipe))
REG_OFFSET         94 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_LP_RX_TIMEOUT_REG(pipe)		(0xb014 + REG_OFFSET(pipe))
REG_OFFSET         95 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_TURN_AROUND_TIMEOUT_REG(pipe)	(0xb018 + REG_OFFSET(pipe))
REG_OFFSET         96 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DEVICE_RESET_TIMER_REG(pipe)	(0xb01c + REG_OFFSET(pipe))
REG_OFFSET         97 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DPI_RESOLUTION_REG(pipe)		(0xb020 + REG_OFFSET(pipe))
REG_OFFSET         98 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DBI_FIFO_THROTTLE_REG(pipe)	(0xb024 + REG_OFFSET(pipe))
REG_OFFSET         99 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HSYNC_COUNT_REG(pipe)		(0xb028 + REG_OFFSET(pipe))
REG_OFFSET        100 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HBP_COUNT_REG(pipe)		(0xb02c + REG_OFFSET(pipe))
REG_OFFSET        101 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HFP_COUNT_REG(pipe)		(0xb030 + REG_OFFSET(pipe))
REG_OFFSET        102 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HACTIVE_COUNT_REG(pipe)		(0xb034 + REG_OFFSET(pipe))
REG_OFFSET        103 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_VSYNC_COUNT_REG(pipe)		(0xb038 + REG_OFFSET(pipe))
REG_OFFSET        104 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_VBP_COUNT_REG(pipe)		(0xb03c + REG_OFFSET(pipe))
REG_OFFSET        105 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_VFP_COUNT_REG(pipe)		(0xb040 + REG_OFFSET(pipe))
REG_OFFSET        106 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe)	(0xb044 + REG_OFFSET(pipe))
REG_OFFSET        107 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DPI_CONTROL_REG(pipe)		(0xb048 + REG_OFFSET(pipe))
REG_OFFSET        108 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DPI_DATA_REG(pipe)			(0xb04c + REG_OFFSET(pipe))
REG_OFFSET        109 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_INIT_COUNT_REG(pipe)		(0xb050 + REG_OFFSET(pipe))
REG_OFFSET        110 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe)	(0xb054 + REG_OFFSET(pipe))
REG_OFFSET        111 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_VIDEO_MODE_FORMAT_REG(pipe)	(0xb058 + REG_OFFSET(pipe))
REG_OFFSET        112 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_EOT_DISABLE_REG(pipe)		(0xb05c + REG_OFFSET(pipe))
REG_OFFSET        113 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_LP_BYTECLK_REG(pipe)		(0xb060 + REG_OFFSET(pipe))
REG_OFFSET        114 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_LP_GEN_DATA_REG(pipe)		(0xb064 + REG_OFFSET(pipe))
REG_OFFSET        115 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HS_GEN_DATA_REG(pipe)		(0xb068 + REG_OFFSET(pipe))
REG_OFFSET        116 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_LP_GEN_CTRL_REG(pipe)		(0xb06c + REG_OFFSET(pipe))
REG_OFFSET        117 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HS_GEN_CTRL_REG(pipe)		(0xb070 + REG_OFFSET(pipe))
REG_OFFSET        118 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_GEN_FIFO_STAT_REG(pipe)		(0xb074 + REG_OFFSET(pipe))
REG_OFFSET        119 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_HS_LS_DBI_ENABLE_REG(pipe)		(0xb078 + REG_OFFSET(pipe))
REG_OFFSET        120 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DPHY_PARAM_REG(pipe)		(0xb080 + REG_OFFSET(pipe))
REG_OFFSET        121 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DBI_BW_CTRL_REG(pipe)		(0xb084 + REG_OFFSET(pipe))
REG_OFFSET        122 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe)	(0xb088 + REG_OFFSET(pipe))
REG_OFFSET        124 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_CTRL_REG(pipe)			(0xb104 + REG_OFFSET(pipe))
REG_OFFSET        125 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DATA_ADD_REG(pipe)			(0xb108 + REG_OFFSET(pipe))
REG_OFFSET        126 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_DATA_LEN_REG(pipe)			(0xb10c + REG_OFFSET(pipe))
REG_OFFSET        127 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_CMD_ADD_REG(pipe)			(0xb110 + REG_OFFSET(pipe))
REG_OFFSET        128 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define MIPI_CMD_LEN_REG(pipe)			(0xb114 + REG_OFFSET(pipe))
REG_OFFSET         83 drivers/pinctrl/spear/pinctrl-plgpio.c 	void __iomem *reg_off = REG_OFFSET(base, reg, pin);
REG_OFFSET         92 drivers/pinctrl/spear/pinctrl-plgpio.c 	void __iomem *reg_off = REG_OFFSET(base, reg, pin);
REG_OFFSET        101 drivers/pinctrl/spear/pinctrl-plgpio.c 	void __iomem *reg_off = REG_OFFSET(base, reg, pin);
REG_OFFSET        340 drivers/pinctrl/spear/pinctrl-plgpio.c 	reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
REG_OFFSET        309 drivers/rtc/rtc-pcf8523.c 	err = pcf8523_read(client, REG_OFFSET, &value);
REG_OFFSET        334 drivers/rtc/rtc-pcf8523.c 	return pcf8523_write(client, REG_OFFSET, value);
REG_OFFSET        763 sound/soc/sh/siu_dai.c 	info->reg = devm_ioremap(&pdev->dev, res->start + REG_OFFSET,
REG_OFFSET        764 sound/soc/sh/siu_dai.c 			    resource_size(res) - REG_OFFSET);