REG_GET_FIELD 125 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 127 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 419 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 2 << REG_GET_FIELD(m->cp_hqd_pq_control, REG_GET_FIELD 681 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { REG_GET_FIELD 685 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { REG_GET_FIELD 686 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) REG_GET_FIELD 693 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) REG_GET_FIELD 157 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 159 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 581 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { REG_GET_FIELD 585 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { REG_GET_FIELD 586 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) REG_GET_FIELD 593 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) REG_GET_FIELD 856 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); REG_GET_FIELD 112 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 114 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, REG_GET_FIELD 577 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { REG_GET_FIELD 581 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { REG_GET_FIELD 582 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) REG_GET_FIELD 589 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) REG_GET_FIELD 320 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 2 << REG_GET_FIELD(m->cp_hqd_pq_control, REG_GET_FIELD 1789 drivers/gpu/drm/amd/amdgpu/cik.c cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); REG_GET_FIELD 1790 drivers/gpu/drm/amd/amdgpu/cik.c cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); REG_GET_FIELD 1807 drivers/gpu/drm/amd/amdgpu/cik.c if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && REG_GET_FIELD 196 drivers/gpu/drm/amd/amdgpu/cz_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { REG_GET_FIELD 336 drivers/gpu/drm/amd/amdgpu/cz_ih.c if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 351 drivers/gpu/drm/amd/amdgpu/cz_ih.c if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 415 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { REG_GET_FIELD 485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), REG_GET_FIELD 632 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) REG_GET_FIELD 666 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { REG_GET_FIELD 431 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { REG_GET_FIELD 511 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), REG_GET_FIELD 658 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) REG_GET_FIELD 692 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { REG_GET_FIELD 1087 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, REG_GET_FIELD 425 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), REG_GET_FIELD 1219 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(adev->gfx.config.gb_addr_config, REG_GET_FIELD 1226 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(adev->gfx.config.gb_addr_config, REG_GET_FIELD 1229 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(adev->gfx.config.gb_addr_config, REG_GET_FIELD 1232 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(adev->gfx.config.gb_addr_config, REG_GET_FIELD 1235 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(adev->gfx.config.gb_addr_config, REG_GET_FIELD 1728 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | REG_GET_FIELD 1729 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); REG_GET_FIELD 2258 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, REG_GET_FIELD 2295 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, REG_GET_FIELD 2332 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, REG_GET_FIELD 2369 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, REG_GET_FIELD 2401 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (REG_GET_FIELD(bootload_status, REG_GET_FIELD 2502 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, REG_GET_FIELD 2572 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, REG_GET_FIELD 2641 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, REG_GET_FIELD 2962 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, REG_GET_FIELD 3887 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), REG_GET_FIELD 3905 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) REG_GET_FIELD 3942 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) REG_GET_FIELD 4058 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; REG_GET_FIELD 4072 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) REG_GET_FIELD 1333 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); REG_GET_FIELD 1539 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; REG_GET_FIELD 4347 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); REG_GET_FIELD 4348 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); REG_GET_FIELD 4351 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); REG_GET_FIELD 4352 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); REG_GET_FIELD 1862 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); REG_GET_FIELD 1863 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); REG_GET_FIELD 1866 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); REG_GET_FIELD 1867 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); REG_GET_FIELD 1886 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); REG_GET_FIELD 3484 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); REG_GET_FIELD 4887 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) REG_GET_FIELD 5001 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) REG_GET_FIELD 5005 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || REG_GET_FIELD 5006 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || REG_GET_FIELD 5007 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) { REG_GET_FIELD 5020 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) REG_GET_FIELD 5023 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY)) REG_GET_FIELD 5052 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || REG_GET_FIELD 5053 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) REG_GET_FIELD 5057 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || REG_GET_FIELD 5058 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || REG_GET_FIELD 5059 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || REG_GET_FIELD 5060 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { REG_GET_FIELD 5152 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || REG_GET_FIELD 5153 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || REG_GET_FIELD 5154 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || REG_GET_FIELD 5155 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { REG_GET_FIELD 5171 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || REG_GET_FIELD 5172 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) REG_GET_FIELD 5605 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) REG_GET_FIELD 5622 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) REG_GET_FIELD 6818 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING); REG_GET_FIELD 6819 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID); REG_GET_FIELD 6829 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW), REG_GET_FIELD 6830 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW), REG_GET_FIELD 6831 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW), REG_GET_FIELD 6832 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP), REG_GET_FIELD 6833 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP), REG_GET_FIELD 6834 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL), REG_GET_FIELD 6835 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT), REG_GET_FIELD 6836 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE) REG_GET_FIELD 6842 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID); REG_GET_FIELD 6843 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID); REG_GET_FIELD 6854 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE); REG_GET_FIELD 6870 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID), REG_GET_FIELD 6871 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID), REG_GET_FIELD 6872 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID), REG_GET_FIELD 6873 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false", REG_GET_FIELD 7125 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; REG_GET_FIELD 1935 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 1944 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 1949 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 1954 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 1959 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 1964 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_GET_FIELD( REG_GET_FIELD 3999 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), REG_GET_FIELD 4046 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) REG_GET_FIELD 4563 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) REG_GET_FIELD 35 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); REG_GET_FIELD 44 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); REG_GET_FIELD 47 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( REG_GET_FIELD 171 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(status, REG_GET_FIELD 174 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(status, REG_GET_FIELD 177 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(status, REG_GET_FIELD 180 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(status, REG_GET_FIELD 183 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(status, REG_GET_FIELD 669 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { REG_GET_FIELD 677 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c size = (REG_GET_FIELD(viewport, REG_GET_FIELD 679 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * REG_GET_FIELD 82 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { REG_GET_FIELD 635 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); REG_GET_FIELD 636 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 641 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 646 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 825 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { REG_GET_FIELD 829 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * REG_GET_FIELD 830 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * REG_GET_FIELD 97 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { REG_GET_FIELD 203 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); REG_GET_FIELD 226 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), REG_GET_FIELD 232 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), REG_GET_FIELD 333 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { REG_GET_FIELD 339 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { REG_GET_FIELD 745 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); REG_GET_FIELD 746 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 752 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 757 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 945 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { REG_GET_FIELD 949 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * REG_GET_FIELD 950 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * REG_GET_FIELD 1272 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 1277 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u32 protections = REG_GET_FIELD(status, REG_GET_FIELD 1282 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c info->mc_id = REG_GET_FIELD(status, REG_GET_FIELD 185 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { REG_GET_FIELD 328 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); REG_GET_FIELD 351 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), REG_GET_FIELD 357 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), REG_GET_FIELD 535 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { REG_GET_FIELD 541 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { REG_GET_FIELD 989 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); REG_GET_FIELD 990 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 996 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 1001 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 1063 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { REG_GET_FIELD 1067 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * REG_GET_FIELD 1068 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * REG_GET_FIELD 1457 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, REG_GET_FIELD 1462 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u32 protections = REG_GET_FIELD(status, REG_GET_FIELD 1467 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c info->mc_id = REG_GET_FIELD(status, REG_GET_FIELD 391 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(status, REG_GET_FIELD 394 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(status, REG_GET_FIELD 397 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(status, REG_GET_FIELD 400 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(status, REG_GET_FIELD 403 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(status, REG_GET_FIELD 1149 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { REG_GET_FIELD 1158 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c size = (REG_GET_FIELD(viewport, REG_GET_FIELD 1160 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(viewport, REG_GET_FIELD 1169 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * REG_GET_FIELD 1170 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * REG_GET_FIELD 196 drivers/gpu/drm/amd/amdgpu/iceland_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { REG_GET_FIELD 336 drivers/gpu/drm/amd/amdgpu/iceland_ih.c if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 351 drivers/gpu/drm/amd/amdgpu/iceland_ih.c if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 217 drivers/gpu/drm/amd/amdgpu/navi10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) REG_GET_FIELD 222 drivers/gpu/drm/amd/amdgpu/navi10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) REG_GET_FIELD 1279 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || REG_GET_FIELD 1280 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { REG_GET_FIELD 1298 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || REG_GET_FIELD 1299 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { REG_GET_FIELD 1377 drivers/gpu/drm/amd/amdgpu/si.c cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); REG_GET_FIELD 1378 drivers/gpu/drm/amd/amdgpu/si.c cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); REG_GET_FIELD 144 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); REG_GET_FIELD 152 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { REG_GET_FIELD 157 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg_c_tx_abrt_source, REG_GET_FIELD 163 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } else if (REG_GET_FIELD(reg_c_tx_abrt_source, REG_GET_FIELD 187 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg_c_tx_abrt_source, REG_GET_FIELD 205 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); REG_GET_FIELD 255 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { REG_GET_FIELD 282 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); REG_GET_FIELD 381 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); REG_GET_FIELD 428 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && REG_GET_FIELD 429 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { REG_GET_FIELD 435 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) { REG_GET_FIELD 444 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg_ic_clr_activity, REG_GET_FIELD 485 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && REG_GET_FIELD 486 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c (REG_GET_FIELD(reg_ic_enable_status, REG_GET_FIELD 871 drivers/gpu/drm/amd/amdgpu/soc15.c cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); REG_GET_FIELD 872 drivers/gpu/drm/amd/amdgpu/soc15.c cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); REG_GET_FIELD 920 drivers/gpu/drm/amd/amdgpu/soc15.c cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); REG_GET_FIELD 921 drivers/gpu/drm/amd/amdgpu/soc15.c cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); REG_GET_FIELD 198 drivers/gpu/drm/amd/amdgpu/tonga_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { REG_GET_FIELD 347 drivers/gpu/drm/amd/amdgpu/tonga_ih.c if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 362 drivers/gpu/drm/amd/amdgpu/tonga_ih.c if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) REG_GET_FIELD 101 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - REG_GET_FIELD 112 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - REG_GET_FIELD 120 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && REG_GET_FIELD 121 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && REG_GET_FIELD 122 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) REG_GET_FIELD 138 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && REG_GET_FIELD 139 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || REG_GET_FIELD 140 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD 141 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || REG_GET_FIELD 142 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || REG_GET_FIELD 143 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) REG_GET_FIELD 183 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && REG_GET_FIELD 184 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || REG_GET_FIELD 185 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { REG_GET_FIELD 189 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); REG_GET_FIELD 190 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); REG_GET_FIELD 1139 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || REG_GET_FIELD 1140 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || REG_GET_FIELD 1460 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || REG_GET_FIELD 1461 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || REG_GET_FIELD 380 drivers/gpu/drm/amd/amdgpu/vega10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) REG_GET_FIELD 395 drivers/gpu/drm/amd/amdgpu/vega10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) REG_GET_FIELD 336 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) REG_GET_FIELD 340 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) REG_GET_FIELD 459 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) REG_GET_FIELD 462 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) REG_GET_FIELD 989 drivers/gpu/drm/amd/amdgpu/vi.c cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); REG_GET_FIELD 990 drivers/gpu/drm/amd/amdgpu/vi.c cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); REG_GET_FIELD 1019 drivers/gpu/drm/amd/amdgpu/vi.c if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && REG_GET_FIELD 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), REG_GET_FIELD 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), REG_GET_FIELD 137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), REG_GET_FIELD 268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), REG_GET_FIELD 150 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), REG_GET_FIELD 1435 drivers/gpu/drm/amd/powerplay/smu_v11_0.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),