REG_GET_4          60 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
REG_GET_4         857 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_GET_4(DCN_EXPANSION_MODE,
REG_GET_4         441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
REG_GET_4        1055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_GET_4(DCN_EXPANSION_MODE,